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ICS84330CYLNT PDF预览

ICS84330CYLNT

更新时间: 2024-11-04 20:19:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
21页 780K
描述
Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, LQFP-32

ICS84330CYLNT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.29
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm湿度敏感等级:3
端子数量:32最高工作温度:70 °C
最低工作温度:最大输出时钟频率:700 MHz
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:25 MHz
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Clock Generators最大压摆率:160 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ICS84330CYLNT 数据手册

 浏览型号ICS84330CYLNT的Datasheet PDF文件第2页浏览型号ICS84330CYLNT的Datasheet PDF文件第3页浏览型号ICS84330CYLNT的Datasheet PDF文件第4页浏览型号ICS84330CYLNT的Datasheet PDF文件第5页浏览型号ICS84330CYLNT的Datasheet PDF文件第6页浏览型号ICS84330CYLNT的Datasheet PDF文件第7页 
700MHz, Low Jitter, Crystal-to-3.3V  
Differential LVPECL Frequency Synthesizer  
ICS84330C  
DATA SHEET  
General Description  
Features  
The ICS84330C is a general purpose, single output  
high frequency synthesizer and a member of the  
HiPerClockS™ family of High Performance Clock  
Solutions from IDT. The VCO operates at a frequency  
range of 250MHz to 700MHz. The VCO and output  
Fully integrated PLL, no external loop filter requirements  
One differential 3.3V LVPECL output  
S
IC  
HiPerClockS™  
Crystal oscillator interface: 10MHz to 25MHz  
Output frequency range: 31.25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
frequency can be programmed using the serial or parallel interfaces  
to the configuration logic. The output can be configured to divide the  
VCO frequency by 1, 2, 4, and 8. Output frequency steps as small as  
250kHz to 2MHz can be achieved using a 16MHz crystal depending  
on the output divider settings.  
Parallel or serial interface for programming M and N dividers during  
power-up  
RMS period jitter: 5ps (maximum)  
Cycle-to-cycle jitter: 40ps (maximum)  
3.3V supply voltage  
Pin Assignment  
0°C to 70°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
32 31 30 29 28 27 26 25  
packages  
1
2
3
4
5
6
7
8
S_CLOCK  
nc  
24  
23  
22  
21  
20  
S_DATA  
S_LOAD  
N1  
N0  
M8  
M7  
ICS84330C  
32 Lead VFQFN  
K Package  
Pin Assignments  
VCCA  
VCCA  
5mm x 5mm x 0.925mm  
package body  
Top View  
25 24 23 22 21 20 19  
FREF_EXT  
XTAL_SEL  
XTAL1  
M6  
M5  
M4  
19  
18  
17  
26  
27  
28  
1
N1  
S_CLOCK  
18  
17  
16  
15  
N0  
M8  
M7  
M6  
S_DATA  
S_LOAD  
ICS84330C  
28 Lead PLCC  
V Package  
9
10 11 12 13 14 15 16  
VCCA  
11.6mm x 11.4mm x 4.1mm  
FREF_EXT  
14  
13  
2
3
4
package body  
Top View  
XTAL_SEL  
XTAL1  
M5  
M4  
Block Diagram  
12  
5
6
7
8
9
10 11  
Pullup  
OE  
XTAL1  
1
0
OSC  
XTAL2  
Pulldown  
FREF_EXT  
÷16  
Pullup  
XTAL_SEL  
32 31 30 29 28 27 26 25  
S_CLOCK  
1
2
3
4
5
6
7
8
nc  
24  
PLL  
S_DATA  
S_LOAD  
23 N1  
ICS84330C  
32 Lead LQFP  
Y Package  
÷2  
PHASEDETECTOR  
÷M  
÷4  
÷8  
÷1  
N0  
22  
1
0
FOUT  
nFOUT  
M8  
21  
VCCA  
VCCA  
VCO  
÷2  
7mm x 7mm x 1.4mm  
package body  
Top View  
M7  
20  
FREF_EXT  
XTAL_SEL  
XTAL1  
M6  
M5  
M4  
19  
18  
17  
Pulldown  
Pulldown  
Pulldown  
Pullup  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
9
10 11 12 13 14 15 16  
Pullup  
Pullup  
M0:M8  
N0:N1  
ICS84330CV REVISION D JULY 17, 2009  
1
©2009 Integrated Device Technology, Inc.  

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