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ICS843404AG PDF预览

ICS843404AG

更新时间: 2024-11-04 11:14:39
品牌 Logo 应用领域
矽成 - ICSI 晶体时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
19页 245K
描述
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR

ICS843404AG 数据手册

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ICS843404  
LVCMOS/CRYSTAL-TO-3.3V LVPECL AND  
LVDS CLOCK GENERATOR  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
The ICS843404 is a low phase noise Fibre  
• Three banks of outputs: one bank of two LVDS outputs  
and two banks of one LVPECL output  
ICS  
Channel Clock Generator and is a member of  
the HiPerClockSTM family of high performance  
clock solutions from ICS. The device provides  
two banks of one LVPECL output per bank and  
HiPerClockS™  
• Selectable crystal oscillator interface or  
LVCMOS/LVTTL single-ended reference clock input  
one bank of two LVDS outputs. Each bank can be  
independently set by using their respective frequency select  
pins for the following output frequencies: 318.75MHz,  
212.5MHz, 159.375MHz or 106.25MHz, using a 25.5MHz  
18pF parallel resonant crystal. The ICS843404 can also be  
driven from a 25.5MHz single-ended reference clock. For  
system debug or test purposes, the PLL can be bypassed  
using the VCO_SEL pin.  
• Four independently selectable output frequency on each  
bank: 318.75MHz, 212.5MHz, 159.375MHz and 106.25MHz  
• Maximum output frequency: 318.75MHz  
• Crystal input frequency: 25.5MHz  
• VDDO_LVPECL can be set for 3.3V or 2.5V, allowing the  
device to generate 3.3V or 2.5V LVPECL levels  
• RMS phase jitter at 106.25MHz, using a 25.5MHz crystal  
(637kHz to 10MHz intergration): 2.65ps (typical)  
PIN ASSIGNMENT  
Offset  
Noise Power  
1
2
3
4
MR  
VCO_SEL  
VDDo_LVDS  
LVDS0  
28  
27  
26  
LVDS_FSEL0  
LVDS_FSEL1  
VDDO_LVPECL  
LVPECLA0  
nLVPECLA0  
LVPECLB0  
nLVPECLB0  
XTAL_SEL  
TEST_CLK  
GND  
100Hz ................. -89.1 dBc/Hz  
1kHz ................. -112.7 dBc/Hz  
10kHz ................. -128.0 dBc/Hz  
100kHz ................. -130.2 dBc/Hz  
25  
nLVDS0  
24  
23  
22  
5
6
7
8
LVDS1  
nLVDS1  
nc  
• Supply voltage modes:  
• VDD = VDDA = 3.3V  
21  
20  
19  
18  
17  
16  
15  
9
LVPECL_FSELB0  
LVPECL_FSELB1  
nc  
VDDA  
LVPECL_FSELA0  
VDD  
• VDDO_LVPECL = 3.3V or 2.5V  
• VDDO_LVDS = 3.3V  
10  
11  
12  
13  
GND  
XTAL_IN  
XTAL_OUT  
LVPECL_FSELA1  
• 0°C to 70°C ambient operating temperature  
14  
• Available in both standard and lead-free RoHS-compliant  
packages  
ICS843404  
• Industrial termperature information available upon request  
28-LeadTSSOP, 173-MIL  
4.4mm x 9.7mm x 0.92mm  
body package  
G Package  
Top View  
BLOCK DIAGRAM  
VDDO_LVPECL  
Pullup  
LVPECL_FSELA1:0  
0 0 ÷2  
VCO_SEL  
LVPECLA0  
0 1 ÷3  
1 0 ÷4  
nLVPECLA0  
1 1 ÷6  
Pulldown  
25.5MHz  
TEST_CLK  
XTAL_IN  
0
1
LVPECL_FSELB1:0  
0 0 ÷2  
0 1 ÷3  
1 0 ÷4  
1 1 ÷6  
0
1
LVPECLB0  
nLVPECLB0  
VCO  
OSC  
Phase  
Detector  
637.5MHz  
(Fixed)  
XTAL_OUT  
XTAL_SEL  
LVDS0  
LVDS_FSEL1:0  
0 0 ÷2  
0 1 ÷3  
1 0 ÷4  
1 1 ÷6  
Pullup  
nLVDS0  
M = 25 (fixed)  
LVDS1  
nLVDS1  
Pulldown  
V
DDO_LVDS  
MR  
843404AG  
www.icst.com/products/hiperclocks.html  
REV.A OCTOBER 17, 2005  
1

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