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ICS840004AG-01LF PDF预览

ICS840004AG-01LF

更新时间: 2024-11-14 03:01:15
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
13页 260K
描述
FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

ICS840004AG-01LF 数据手册

 浏览型号ICS840004AG-01LF的Datasheet PDF文件第2页浏览型号ICS840004AG-01LF的Datasheet PDF文件第3页浏览型号ICS840004AG-01LF的Datasheet PDF文件第4页浏览型号ICS840004AG-01LF的Datasheet PDF文件第5页浏览型号ICS840004AG-01LF的Datasheet PDF文件第6页浏览型号ICS840004AG-01LF的Datasheet PDF文件第7页 
PRELIMINARY  
ICS840004-01  
Integrated  
Circuit  
Systems, Inc.  
FEMTOCLOCKS™ CRYSTAL-TO-  
LVCMOS/LVTTL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
• Four LVCMOS/LVTTL outputs,  
The ICS840004-01 is a 4 output LVCMOS/LVTTL  
ICS  
HiPerClockS™  
15Ω typical output impedance  
• Selectable crystal oscillator interface  
or LVCMOS/LVTTL single-ended input  
Synthesizer optimized to generate Ethernet  
reference clock frequencies and is a member of  
the HiPerClocksTM family of high performance  
clock solutions from ICS. Using a 25MHz, 18pF  
• Output frequency Range: 56MHz - 175MHz  
• VCO Range: 560MHz - 700MHz  
parallel resonant crystal, the following frequencies can be  
generated based on the 2 frequency select pins (F_SEL1:0):  
156.25MHz, 125MHz, and 62.5MHz.The ICS840004-01 uses  
ICS’ 3rd generation low phase noise VCO technology and can  
achieve 1ps or lower typical random rms phase jitter, easily  
meeting Ethernet jitter requirements. The ICS840004-01 is  
packaged in a small 20-pin TSSOP package.  
• RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):  
0.52ps (typical) design target  
Phase noise:  
Offset  
Noise Power  
100Hz ............... -94.9 dBc/Hz  
1kHz ............. -119.6 dBc/Hz  
10kHz ............. -128.9 dBc/Hz  
100kHz ............. -129.2 dBc/Hz  
• Full 3.3V or 3.3V core/2.5V output supply mode  
• 0°C to 70°C ambient operating temperature  
• Available in both standard and lead-free RoHS-compliant  
packages  
FREQUENCY SELECT FUNCTION TABLE FOR ETHERNET FREQUENCIES  
Inputs  
M Divider N Divider  
Value  
Output Frequency  
(25MHz Ref.)  
M/N  
Ratio Value  
F_SEL1 F_SEL0  
Value  
0
0
1
1
0
1
0
1
25  
4
6.25  
156.25  
125  
25  
25  
25  
5
10  
5
5
2.5  
5
62.5  
125  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Pullup  
OE  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
F_SEL0  
nc  
F_SEL1  
GND  
Q0  
2
3
4
5
6
7
8
9
2
Pullup:Pullup  
F_SEL1:0  
nXTAL_SEL  
TEST_CLK  
OE  
MR  
nPLL_SEL  
VDDA  
Q1  
VDDO  
Q2  
Q3  
GND  
XTAL_IN  
XTAL_OUT  
Pulldown  
nPLL_SEL  
Pulldown  
nXTAL_SEL  
25MHz  
XTAL_IN  
nc  
VDD  
F_SEL1:0  
0
Q0  
Q1  
10  
OSC  
1
N
0 0 ÷4  
XTAL_OUT  
Pulldown  
ICS840004-01  
20-LeadTSSOP  
6.5mm x 4.4mm x 0.92mm  
package body  
0 1 ÷5  
1 0 ÷10  
1 1 ÷5  
Phase  
Detector  
1
TEST_CLK  
VCO  
0
Q2  
Q3  
G Package  
TopView  
M = ÷25 (fixed)  
Pulldown  
MR  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on  
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications  
without notice.  
840004AG-01  
www.icst.com/products/hiperclocks.html  
REV.B JANUARY 3, 2006  
1

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