PRELIMINARY
ICS840004
Integrated
Circuit
Systems, Inc.
FEMTO
CLOCKS™ CRYSTAL- -
TO
LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS840004 is a 4 output LVCMOS/LVTTL • Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
ICS
Synthesizer optimized to generate Ethernet
• Selectable crystal oscillator interface
HiPerClockS™
reference clock frequencies and is a member of
or LVCMOS single-ended input
the HiPerClocksTM family of high performance
• Supports the following input frequencies:
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz and
53.125MHz
clock solutions from ICS. Using a 26.5625MHz,
18pF parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and
53.125MHz.The ICS840004 uses ICS’3rd generation low phase
noise VCO technology and can achieve 1ps or lower typical
random rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS840004 is packaged in a small 20-pin
TSSOP package.
• RMS phase jitter @ 212.5MHz (637KHz - 10MHz):
0.98ps typical
• RMS phase noise at 212.5MHz, VDDO = 3.3V
Phase noise:
Offset
Noise Power
100Hz ............... -88.8 dBc/Hz
1KHz ..............-109.0 dBc/Hz
10KHz ..............-116.1 dBc/Hz
100KHz ..............-117.5 dBc/Hz
• Full 3.3V or 3.3V core/2.5V output supply mode
• 0°C to 70°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Inputs
Output
Frequency
Range
Input
Frequency
M Divider N Divider
M/N
Ratio Value
F_SEL1 F_SEL0
Value
Value
26.5625
26.5625
26.5625
26.5625
26.04166
0
0
1
1
0
0
1
0
1
1
24
3
8
6
4
2
6
212.5
159.375
106.25
53.125
156.25
24
24
24
24
4
6
12
4
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
20
19
18
17
16
15
14
13
12
11
F_SEL0
nc
F_SEL1
GND
Q0
2
3
4
5
6
7
8
9
2
Pulldown:Pulldown
F_SEL1:0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
Pulldown
nPLL_SEL
Pulldown
nXTAL_SEL
26.5625MHz
XTAL_IN
nc
VDD
F_SEL1:0
0
Q0
Q1
10
OSC
1
0
N
0 0 ÷3
XTAL_OUT
Pulldown
ICS840004
20-LeadTSSOP
6.5mm x 4.4mm x 0.92mm
package body
0 1 ÷4
Phase
Detector
1
TEST_CLK
VCO
1 0 ÷6 (default)
1 1 ÷12
Q2
Q3
G Package
Top View
M = ÷24 (fixed)
Pulldown
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840004AG
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 16, 2004
1