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ICS83940AYLF PDF预览

ICS83940AYLF

更新时间: 2024-11-21 14:42:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
14页 170K
描述
Low Skew Clock Driver, 18 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

ICS83940AYLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.18输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:18
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):5.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:200 MHzBase Number Matches:1

ICS83940AYLF 数据手册

 浏览型号ICS83940AYLF的Datasheet PDF文件第2页浏览型号ICS83940AYLF的Datasheet PDF文件第3页浏览型号ICS83940AYLF的Datasheet PDF文件第4页浏览型号ICS83940AYLF的Datasheet PDF文件第5页浏览型号ICS83940AYLF的Datasheet PDF文件第6页浏览型号ICS83940AYLF的Datasheet PDF文件第7页 
PRELIMINARY  
ICS83940  
Integrated  
Circuit  
Systems, Inc.  
LOW SKEW, 1-TO-18  
LVPECL-TO-LVCMOS FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS83940 is a low skew, 1-to-18 LVPECL-  
18 LVCMOS outputs, 23typical output impedance  
Selectable LVCMOS_CLK or LVPECLclock inputs  
to-LVCMOS Fanout Buffer and a member of the  
HiPerClockS™ family of High Performance Clock  
Solutions from ICS. The ICS83940 has two se-  
lectable clock inputs. The PCLK, nPCLK pair can  
HiPerClockS™  
PCLK, nPCLK supports the following input types:  
LVPECL, CML, SSTL  
accept LVPECL, CML, or SSTL input levels. The  
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.  
The low impedance LVCMOS outputs are designed to drive  
50series or parallel terminated transmission lines.  
LVCMOS_CLK accepts the following input levels:  
LVCMOS or LVTTL  
Maximum output frequency up to 250MHz  
Output skew: 150ps (maximum)  
The ICS83940 is characterized at full 3.3V, full 2.5V and mixed  
3.3V input and 2.5V output operating supply modes. Guaran-  
teed output and part-to-part skew characteristics make the  
ICS83940 ideal for those clock distribution applications de-  
manding well defined performance and repeatability.  
Part to part skew: 750ps (maximum)  
Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
Pin compatible with the MPC940L  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
32 31 30 29 28 27 26 25  
PCLK  
0
Q6  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
3
4
5
6
7
8
GND  
GND  
nPCLK  
18  
Q7  
Q0 - Q17  
Q8  
1
LVCMOS_CLK  
LVCMOS_CLK  
CLK_SEL  
PCLK  
VDD  
Q9  
ICS83940  
Q10  
Q11  
GND  
nPCLK  
VDD  
VDDO  
9
10 11 12 13 14 15 16  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Pacakge  
Top View  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
83940AY  
www.icst.com/products/hiperclocks.html  
REV. D DECEMBER 21, 2001  
1

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