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ICS83940DI PDF预览

ICS83940DI

更新时间: 2024-11-25 11:14:35
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
13页 109K
描述
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

ICS83940DI 数据手册

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ICS83940DI  
LOW SKEW, 1-TO-18  
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER  
Integrated  
Circuit  
Systems, Incꢀ  
GENERAL DESCRIPTION  
FEATURES  
The ICS83940DI is a low skew, 1-to-18 LVPECL-  
18 LVCMOS/LVTTLoutputs  
to-LVCMOS/LVTTL Fanout Buffer and a member  
Selectable LVCMOS_CLK or LVPECLclock inputs  
HiPerClockS™  
of the HiPerClockS™ family of High Performance  
Clock Solutions from ICS. The ICS83940DI has  
two selectable clock inputs. The PCLK, nPCLK  
PCLK, nPCLK supports the following input types:  
LVPECL, CML, SSTL  
pair can accept LVPECL, CML, or SSTL input levels. The  
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.  
The low impedance LVCMOS/LVTTL outputs are designed to  
drive 50series or parallel terminated transmission lines.  
LVCMOS_CLK accepts the following input levels:  
LVCMOS or LVTTL  
Maximum output frequency: 250MHz  
Output skew: 150ps (maximum)  
The ICS83940DI is characterized at 3.3V, 2.5V or mixed  
3.3V core, 2.5V output operating supply modes. Guaranteed  
output and part-to-part skew characteristics make the  
ICS83940DI ideal for those clock distribution applications  
demanding well defined performance and repeatability.  
Part to part skew: 750ps (maximum)  
3.3V, 2.5V or mixed 3.3V core, 2.5V output supply modes  
-40°C to 85°C ambient operating temperature  
Pin compatible with the MPC940L  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
32 31 30 29 28 27 26 25  
PCLK  
0
Q6  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
3
4
5
6
7
8
GND  
GND  
nPCLK  
18  
Q7  
Q0:Q17  
Q8  
1
LVCMOS_CLK  
LVCMOS_CLK  
CLK_SEL  
PCLK  
VDD  
Q9  
ICS83940DI  
10 11 12 13 14 15 16  
32-Lead LQFP  
Q10  
Q11  
GND  
nPCLK  
VDD  
VDDO  
9
7mm x 7mm x 1.4mm package body  
Y Pacakge  
Top View  
83940DYI  
www.icst.com/products/hiperclocks.html  
REV. A DECEMBER 12, 2002  
1

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