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ICS275GILF PDF预览

ICS275GILF

更新时间: 2024-10-28 07:58:39
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
9页 197K
描述
Clock Generator, CMOS, PDSO16

ICS275GILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:End Of Life包装说明:TSSOP, TSSOP16,.25
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.52
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
湿度敏感等级:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
子类别:Clock Generators标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
Base Number Matches:1

ICS275GILF 数据手册

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DATASHEET  
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER  
ICS275  
Description  
Features  
The ICS275 field programmable VCXO clock synthesizer  
generates up to four high-quality, high-frequency clock  
outputs including multiple reference clocks from a  
low-frequency crystal input. It is designed to replace  
crystals and crystal oscillators in most electronic systems.  
Packaged as 16-pin TSSOP  
Eight addressable registers  
Replaces multiple crystals and oscillators  
Output frequencies up to 200 MHz at 3.3 V  
Input crystal frequency of 5 to 27 MHz  
Up to four reference outputs  
Up to two sets of two low-skew outputs  
Operating voltages of 3.3 V  
Controllable output drive levels  
TM  
Using ICS’ VersaClock software to configure PLLs and  
outputs, the ICS275 contains a One-Time Programmable  
(OTP) ROM for field programmability. Programming  
features include VCXO, eight selectable configuration  
registers and up to two sets of two low-skew outputs.  
Advanced, low-power CMOS process  
Available in RoHS compliant packaging  
Using Phase-Locked Loop (PLL) techniques, the device  
runs from a standard fundamental mode, inexpensive  
crystal, or clock. It can replace VCXOs, multiple crystals  
and oscillators, saving board space and cost.  
The ICS275 is also available in factory programmed custom  
versions for high-volume applications.  
Block Diagram  
3
VDD  
3
OTP  
PLL1  
PLL2  
S2:S0  
CLK1  
CLK2  
CLK3  
CLK4  
ROM  
with  
PLL  
Divide  
Logic  
and  
Output  
Enable  
Control  
Values  
VIN  
PLL3  
X1  
X2  
Voltage  
Controlled  
Crystal  
Crystal  
Oscillator  
GND  
2
External capacitors  
are required.  
PDTS  
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 1  
ICS275  
REV C 061206  

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