Datasheet > 存储 > DRAM> IC41LV16105S-50TI

IC41LV16105S-50TI

更新时间： 2024-02-03 03:59:27

品牌	Logo	应用领域
矽成 - ICSI		存储内存集成电路光电二极管动态存储器
页数	文件大小	规格书
18页	199K
描述
1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

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IC41LV16105S-50TI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	0.400 INCH, TSOP2-50/44	Reach Compliance Code：	compliant
风险等级：	5.83	访问模式：	FAST PAGE
最长访问时间：	50 ns	其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G44
JESD-609代码：	e0	内存密度：	16777216 bit
内存集成电路类型：	FAST PAGE DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	44	字数：	1048576 words
字数代码：	1000000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	1MX16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	TSOP44/50,.46,32	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	1024
自我刷新：	YES	最大待机电流：	0.0005 A
子类别：	DRAMs	最大压摆率：	0.16 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
Base Number Matches：	1

IC41LV16105S-50TI 数据手册

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IC41C16105S

IC41LV16105S

ꢀunctional Description

Write Cycle

The IC41C16105S and IC41LV16105S is a CMOS DRAM

optimized for high-speed bandwidth, low power

applications. During READ or WRITE cycles, each bit is

uniquely addressed through the 10 address bits. These

are entered ten bits (A0-A9) at a time. The row address is

latched by the Row Address Strobe (RAS). The column

address is latched by the Column Address Strobe (CAS).

RAS is used to latch the first ten bits and CAS is used the

latter ten bits.

A write cycle is initiated by the falling edge of CAS and WE,

whichever occurs last. The input data must be valid at or

before the falling edge of CAS or WE, whichever occurs

last.

Refresh Cycle

To retain data, 1,024 refresh cycles are required in each

16 ms period. There are two ways to refresh the memory.

1. By clocking each of the 1,024 row addresses (A0

through A9) with RAS at least once every 16 ms. Any

read, write, read-modify-write or RAS-only cycle re-

freshes the addressed row.

The ICS41C16105S and IC41LV16105S has two CAS

controls, LCAS and UCAS. The LCAS and UCAS inputs

internally generates a CAS signal functioning in an iden-

tical manner to the single CAS input on the other 1M x 16

DRAMs. The key difference is that each CAS controls its

corresponding I/O tristate logic (in conjunction with OE

and WE and RAS). LCAS controls I/O0 through I/O7 and

UCAS controls I/O8 through I/O15.

2. Using a CAS-before-RAS refresh cycle. CAS-before-

RAS refresh is activated by the falling edge of RAS,

while holding CAS LOW. In CAS-before-RAS refresh

cycle, an internal 10-bit counter provides the row

addresses and the external address inputs are ignored.

The IC41C16105S and IC41LV16105S CAS function is

determined by the first CAS (LCAS or UCAS) transitioning

LOW and the last transitioning back HIGH. The two CAS

controls give the IS41C16105L and IS41LV16105L both

BYTE READ and BYTE WRITE cycle capabilities.

CAS-before-RAS is a refresh-only mode and no data

access or device selection is allowed. Thus, the output

remains in the High-Z state during the cycle.

Self Refresh Cycle

The Self Refresh allows the user a dynamic refresh, data

retention mode at the extended refresh period of 128 ms.

i.e., 125 µs per row when using distributed CBR refreshes.

The feature also allows the user the choice of a fully static,

low power data retention mode. The optional Self Refresh

feature is initiated by performing a CBR Refresh cycle and

holding RAS LOW for the specified t^RAS.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is

terminated by returning both RAS and CAS HIGH. To

ensures proper device operation and data integrity any

memory cycle, once initiated, must not be ended or

aborted before the minimum t^RAStime has expired. A new

cycle must not be initiated until the minimum precharge

time tRP, tCP has elapsed.

The Self Refresh mode is terminated by driving RAS HIGH

for a minimum time of t^RP. This delay allows for the

completion of any internal refresh cycles that may be in

process at the time of the RAS LOW-to-HIGH transition. If

the DRAM controller uses a distributed refresh sequence,

a burst refresh is not required upon exiting Self Refresh.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH. The

column address must be held for a minimum time specified

by t^AR. Data Out becomes valid only when tRAC, tAA, tCAC

and tOEA are all satisfied. As a result, the access time is

dependent on the timing relationships between these

parameters.

However, if the DRAM controller utilizes a RAS-only or

burst refresh sequence, all 1,024 rows must be refreshed

within the average internal refresh rate, prior to the re-

sumption of normal operation.

Power-On

After application of the VCC supply, an initial pause of

200 µs is required followed by a minimum of eight initial-

ization cycles (any combination of cycles containing a

RAS signal).

During power-on, it is recommended that RAS track with

V^CCor be held at a valid VIH to avoid current surges.

Integrated Circuit Solution Inc.

DR011-0A 05/23/2001

1 2 345 6 7...18

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与IC41LV16105S-50TI相关器件

型号	品牌	描述	获取价格	数据表
IC41LV16105S-60K	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE	获取价格
IC41LV16105S-60K	ISSI	Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO42, 0.400 INCH, SOJ-42	获取价格
IC41LV16105S-60KI	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE	获取价格
IC41LV16105S-60KI	ISSI	Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO42, 0.400 INCH, SOJ-42	获取价格
IC41LV16105S-60T	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE	获取价格
IC41LV16105S-60T	ISSI	Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44,	获取价格

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