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IBM21S650PFA PDF预览

IBM21S650PFA

更新时间: 2024-02-16 21:30:06
品牌 Logo 应用领域
国际商业机器公司 - IBM 局域网数据传输PC外围集成电路
页数 文件大小 规格书
86页 804K
描述
LAN Controller, 0 Channel(s), 50MBps, CMOS, PQFP144, 20 X 20 MM, LQFP-144

IBM21S650PFA 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:144
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.84地址总线宽度:32
边界扫描:YES总线兼容性:PCI
数据编码/解码方法:NRZ最大数据传输速率:50 MBps
外部数据总线宽度:32JESD-30 代码:S-PQFP-G144
长度:20 mm低功率模式:YES
串行 I/O 数:端子数量:144
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1.7 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:20 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

IBM21S650PFA 数据手册

 浏览型号IBM21S650PFA的Datasheet PDF文件第2页浏览型号IBM21S650PFA的Datasheet PDF文件第3页浏览型号IBM21S650PFA的Datasheet PDF文件第4页浏览型号IBM21S650PFA的Datasheet PDF文件第5页浏览型号IBM21S650PFA的Datasheet PDF文件第6页浏览型号IBM21S650PFA的Datasheet PDF文件第7页 
IBM21S650PFA  
1394 Serial Bus Link Layer PCI Controller  
Features  
• Fully IEEE 1394-1995 compatible  
• General purpose IEEE 1394 Host Controller  
• Asynchronous and isochronous capability  
• Data rates: S100, S200, or S400Mb/s  
• Uses DB DMA channel programs to communi-  
cate with the device driver.  
• Cycle Master capable  
• ROM interface for external configuration ROM  
• PCI 2.1 compatible, with master and slave capa-  
bilities  
• Standard Link-PHY protocol and an Isolation  
barrier between the link controller and the PHY  
as described in IEEE 1394 Specification,  
Annex J  
• 33MHz PCI bus support  
• Parity error detection and report  
• CMOS5S technology  
Transmits and receives packets larger than the  
2KB internal buffer size.  
• 3.3V power supply with 5.0V tolerant I/O  
• 144 pin LQFP package  
• Supports data chaining for packets and indi-  
cates status of each package  
Description  
The IBM21S650PFA is a generic Link Layer Control-  
ler for the 1394 serial bus using a PCI system inter-  
face. It supports the transaction and bus  
PCI to 1394 Interface System Example  
management layers with an additional PHY device  
and includes a DMA engine to reduce the CPU inter-  
vention in transmitted or received packets.  
CPU  
Host Bridge  
DRAM  
PCI Bus  
This link controller transmits and receives all types  
of asynchronous packets, including cable physical  
layer packets. It supports four isochronous DMA  
channels, each of which can be programmed for  
transmit or receive operation.  
• Supports Packet-by-Packet and Contiguous  
modes in receive.  
• Supports Scatter & Gather of data in transmit  
and receive operations.  
Link Controller  
PCI Component  
PHY  
1394 Bus  
1394  
1394  
device  
1394  
device  
1394  
device  
1394  
device  
• Supports starting/stopping the channel opera-  
tion.  
device  
• Supports cycle count information per packet for  
receive.  
The IBM21S650PFA has additional features. It can  
function as PCI master, supporting cache line com-  
mands, or as a PCI slave, supporting memory or  
configuration access as a medium speed target.  
During a 1394 bus reset, it receives the Self ID  
packets from the PHY and forwards them to the sys-  
tem memory. The link controller also has an external  
port that allows direct access from the host CPU to  
an expansion ROM or configuration ROM.  
©IBM Corporation 1997, 1998. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
21S650pfa.00  
12/18/98  
Page 1 of 86  

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