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HYMD232646AL8-K PDF预览

HYMD232646AL8-K

更新时间: 2024-11-11 05:37:15
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
16页 234K
描述
Unbuffered DDR SDRAM DIMM

HYMD232646AL8-K 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM184针数:184
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:SINGLE BANK PAGE BURST最长访问时间:0.75 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N184
内存密度:2147483648 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:184
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM184
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:2.5 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.16 A子类别:DRAMs
最大压摆率:2.44 mA最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

HYMD232646AL8-K 数据手册

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32Mx64 bits  
Unbuffered DDR SDRAM DIMM  
HYMD232646A(L)8-M/K/H/L  
DESCRIPTION  
Hynix HYMD232646A(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line  
Memory Modules(DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232646A(L)8-M/  
K/H/L series consists of eight 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy sub-  
strate.Hynix HYMD232646A(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor  
of industry standard. It is suitable for easy interchange and addition.  
Hynix HYMD232646A(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous  
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs  
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-  
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.  
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and  
burst lengths allow variety of device operation in high performance memory system.  
Hynix HYMD232646A(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is  
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify  
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.  
FEATURES  
256MB (32M x 64) Unbuffered DDR DIMM based on  
32Mx8 DDR SDRAM  
Data inputs on DQS centers when write (centered  
DQ)  
JEDEC Standard 184-pin dual in-line memory mod-  
ule (DIMM)  
Data strobes synchronized with output data for read  
and input data for write  
2.5V +/- 0.2V VDD and VDDQ Power supply  
Programmable CAS Latency 2 / 2.5 supported  
All inputs and outputs are compatible with SSTL_2  
interface  
Programmable Burst Length 2 / 4 / 8 with both  
sequential and interleave mode  
Fully differential clock operations (CK & /CK) with  
100MHz/125MHz/133MHz  
tRAS Lock-out function supported  
Internal four bank operations with single pulsed RAS  
Auto refresh and self refresh supported  
8192 refresh cycles / 64ms  
All addresses and control inputs except Data, Data  
strobes and Data masks latched on the rising edges  
of the clock  
Data(DQ), Data strobes and Write masks latched on  
both rising and falling edges of the clock  
ORDERING INFORMATION  
Part No.  
Power Supply  
Clock Frequency  
Interface  
Form Factor  
HYMD232646A(L)8-M  
HYMD232646A(L)8-K  
HYMD232646A(L)8-H  
HYMD232646A(L)8-L  
133MHz (*DDR266:2-2-2)  
133MHz (*DDR266A)  
133MHz (*DDR266B)  
100MHz (*DDR200)  
VDD=2.5V  
VDDQ=2.5V  
184pin Unbuffered DIMM  
5.25 x 1.25 x 0.15 inch  
SSTL_2  
* JEDEC Defined Specifications compliant  
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev. 0.3/Jul. 02  
1

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