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HYB25M144180C-653 PDF预览

HYB25M144180C-653

更新时间： 2024-01-15 02:18:50
品牌 Logo 应用领域
其他 - ETC 内存集成电路动态存储器时钟
页数 文件大小 规格书
92页 910K
描述
RAMBUS DRAM

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中文翻译

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HYB25M144180C-653 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：TBGA, BGA62,12X9,40/32
针数：62Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.24
风险等级：5.92Is Samacsys：N
访问模式：BLOCK ORIENTED PROTOCOL最长访问时间：53 ns
其他特性：SELF CONTAINED REFRESH最大时钟频率 (fCLK)：600 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B62
JESD-609代码：e0长度：11 mm
内存密度：150994944 bit内存集成电路类型：RAMBUS DRAM
内存宽度：18功能数量：1
端口数量：1端子数量：62
字数：8388608 words字数代码：8000000
工作模式：SYNCHRONOUS组织：8MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA62,12X9,40/32
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8/2.5,2.5 V
认证状态：Not Qualified刷新周期：16384
反向引出线：YES座面最大高度：1.05 mm
自我刷新：YES子类别：DRAMs
最大供电电压 (Vsup)：2.63 V最小供电电压 (Vsup)：2.37 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10.5 mmBase Number Matches：1

HYB25M144180C-653 数据手册

 浏览型号HYB25M144180C-653的Datasheet PDF文件第2页浏览型号HYB25M144180C-653的Datasheet PDF文件第3页浏览型号HYB25M144180C-653的Datasheet PDF文件第4页浏览型号HYB25M144180C-653的Datasheet PDF文件第5页浏览型号HYB25M144180C-653的Datasheet PDF文件第6页浏览型号HYB25M144180C-653的Datasheet PDF文件第7页 
Direct RDRAM  
128/144-MBit (256K×16/18×32s)  
Overview  
The Rambus Direct RDRAM is a general purpose high-performance memory device suitable for  
use in a broad range of applications including computer memory, graphics, video, and any other  
application where high bandwidth and low latency are required.  
The 128/144-Mbit Direct Rambus DRAMs (RDRAM ) are extremely high-speed CMOS DRAMs  
organized as 8M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology  
permits 600 MHz to 800 MHz transfer rates while using conventional system and board design  
technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two  
bytes (10 ns per sixteen bytes).  
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple,  
simultaneous randomly addressed memory transactions. The separate control and data buses with  
independent row and column control yield over 95% bus efficiency. The Direct RDRAM’s thirty-two  
banks support up to four simultaneous transactions.  
System oriented features for mobile, graphics and large memory systems include power  
management, byte masking, and x18 organization. The two data bits in the x18 organization are  
general and can be used for additional storage and bandwidth or for error correction.  
Features  
• Highest sustained bandwidth per DRAM device  
– 1.6 GB/s sustained data transfer rate  
– Separate control and data buses for maximized efficiency  
– Separate row and column control buses for easy scheduling and highest performance  
– 32 banks: four transactions can take place simultaneously at full bandwidth data rates  
• Low latency features  
– Write buffer to reduce read latency  
– 3 precharge mechanisms for controller flexibility  
– Interleaved transactions  
• Advanced power management:  
– Multiple low power states allows flexibility in power consumption versus time to transition to  
active state  
– Power-down self-refresh  
• Organization: 1 Kbyte pages and 32 banks, x16/18  
– x18 organization allows ECC configurations or increased storage/bandwidth  
– x16 organization for low cost applications  
• Uses Rambus Signaling Level (RSL) for up to 800 MHz operation  
• The ODF function is allready implemented in this device and will be described in a later  
version of this document  
INFINEON Technologies  
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