Direct RDRAM™
®
72-Mbit (256Kx16/18x16d)
RAMBUS
Overview
The Rambus Direct RDRAM™ is a general purpose
high-performance memory device suitable for use in a
broad range of applications including computer
memory, graphics, video, and any other application
where high bandwidth and low latency are required.
The 72-Mbit Direct Rambus DRAMs (RDRAM ) are
extremely high-speed CMOS DRAMs organized as 4M
words by 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 600MHz to 800MHz transfer
rates while using conventional system and board
design technologies. Direct RDRAM devices are
capable of sustained data transfers at 1.25 ns per two
bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the
highest sustained bandwidth for multiple, simulta-
neous randomly addressed memory transactions. The
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
Direct RDRAM's sixteen banks support up to four
simultaneous transactions.
Figure 1: Direct RDRAM CSP Package
The 72-Mbit Direct RDRAMs are offered in a CSP hori-
zontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
System oriented features for mobile, graphics and large
memory systems include power management, byte
masking, and x18 organization. The two data bits in the
x18 organization are general and can be used for addi-
tional storage and bandwidth or for error correction.
Direct RDRAMs operate from a 2.5 volt supply.
Key Timing Parameters/Part Number
I/O Freq.
MHz
Part
Number
Organization
trac
Features
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
4M x 18
600
600
711
711
800
800
53 ns HYB25R72180C-653
45 ns HYB25R72180C-745
50 ns HYB25R72180C-750
45 ns HYB25R72180C-645
45 ns HYB25R72180C-845
40 ns HYB25R72180C-840
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Highest sustained bandwidth per DRAM device
- 1.6GB/ s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 16 banks: four transactions can take place simul-
taneously at full bandwidth data rates
■
■
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in
power consumption versus time to transition to
active state
- Power-down self-refresh
■
■
Organization: 1Kbyte pages and 16 banks, x 18
- x18 organization allows ECC configurations or
increased storage/ bandwidth
Uses Rambus Signaling Level (RSL) for up to
800MHz operation
INFINEON Technologies Version 1.0
Preliminary Information
Page 1