Datasheet > HY62256ALP-I

HY62256ALP-I

更新时间： 2022-11-27 00:26:18

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HY62256ALP-I 数据手册

-sram/62256alt1

http://www.hea.com/hean2/sram/62256alt1.htm

HYUNDAI ELECTRONICS AMERICA

HY62256A-I

TIMING INFORMATION

32K x 8bit CMOS SRAM

TIMING DIAGRAM

READ CYCLE 1

Note (READ CYCLE):

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open

circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min.

both for a given device and from device to device.

3. /WE is high for the read cycle.

READ CYCLE 2

Note (READ CYCLE):

1. /WE is high for the read cycle.

2. Device is continuously selected /CS= VIL.

3. /OE =VIL.

WRITE CYCLE 1 (/OE Clocked)

1 of 3

22/10/97 12:35

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