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HY62256ALLJ

更新时间： 2022-11-25 11:07:24

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HY62256ALLJ 数据手册

-sram/62256alt1

http://www.hea.com/hean2/sram/62256alt1.htm

WRITE CYCLE 2 (/OE Low Fixed)

Notes (WRlTE CYCLE):

1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at

the latest transition among /CS going low and /WE going low: A write ends at

the earliest transition among /CS going high and /WE going high. tWP is

measured from the beginning of write to the end of write.

2. tcw is measured from the later of /CS going low to the end of write .

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in

case a write ends as /CS, or /WE going high.

5. If /OE and /WE are in the read mode during this period, and the I/O pins are in

the output low-Z state, input of opposite phase of the output must not be applied

because bus contention can occur.

6. If /CS goes low simultaneously with /WE going low, or after /WE going low,

the outputs remain in high impedance state.

7. DOUT is the same phase of latest written data in this write cycle.

8. DOUT is the read data of the new address.

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22/10/97 12:35

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型号	品牌	描述	获取价格	数据表
HY62256ALLJ-10	HYNIX	Standard SRAM, 32KX8, 100ns, CMOS, PDSO28, 0.330 INCH, SOP-28	获取价格
HY62256ALLJ-12	ETC	x8 SRAM	获取价格
HY62256ALLJ-120	HYNIX	Standard SRAM, 32KX8, 120ns, CMOS, PDSO28, 0.330 INCH, SOP-28	获取价格
HY62256ALLJ-55	ETC	x8 SRAM	获取价格
HY62256ALLJ-55I	HYNIX	Standard SRAM, 32KX8, 55ns, CMOS	获取价格
HY62256ALLJ-70	ETC	x8 SRAM	获取价格