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HY62256ALLJ PDF预览

HY62256ALLJ

更新时间: 2022-11-25 11:07:24
品牌 Logo 应用领域
海力士 - HYNIX 静态存储器
页数 文件大小 规格书
14页 822K
描述
32Kx8bit CMOS SRAM

HY62256ALLJ 数据手册

 浏览型号HY62256ALLJ的Datasheet PDF文件第4页浏览型号HY62256ALLJ的Datasheet PDF文件第5页浏览型号HY62256ALLJ的Datasheet PDF文件第6页浏览型号HY62256ALLJ的Datasheet PDF文件第8页浏览型号HY62256ALLJ的Datasheet PDF文件第9页浏览型号HY62256ALLJ的Datasheet PDF文件第10页 
-sram/62256ala1  
http://www.hea.com/hean2/sram/62256ala1.htm  
AC CHARACTERISTICS  
Vcc = 5V(±)10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.) unless otherwise  
specified.  
-55  
-70  
-85  
# Symbol  
Parameter  
Unit  
Min. Max. Min. Max. Min. Max.  
READ CYCLE  
1 tRC  
2 tAA  
3 tACS  
Read Cycle Time  
55  
-
-
70  
-
-
85  
-
-
ns  
ns  
ns  
Address Access Time  
55  
55  
70  
70  
85  
85  
Chip Select Access Time  
-
-
-
Output Enable to Output  
Valid  
4 tOE  
-
30  
-
-
35  
-
-
45  
-
ns  
ns  
ns  
ns  
ns  
ns  
Chip Select to Output in  
Low Z  
5 tCLZ  
6 tOLZ  
7 tCHZ  
8 tOHZ  
9 tOH  
5
5
0
0
5
5
5
0
0
5
5
5
0
0
5
Output Enable to Output in  
Low Z  
-
-
-
Chip Deselection to Output  
in High Z  
20  
20  
-
30  
30  
-
30  
30  
-
Out Disable to Output in  
High Z  
Output Hold from Address  
Change  
WRITE CYCLE  
10 tWC  
Write Cycle Time  
55  
50  
-
-
70  
65  
-
-
85  
75  
-
-
ns  
ns  
Chip Selection to End of  
Write  
11 tCW  
Address Valid to End of  
Write  
12 tAW  
50  
-
65  
-
75  
-
ns  
13 tAS  
14 tWP  
15 tWR  
Address Set-up Time  
Write Pulse Width  
0
-
0
-
0
-
ns  
ns  
ns  
ns  
ns  
ns  
40  
0
-
50  
0
-
55  
0
-
Write Recovery Time  
-
-
-
16 tWHZ Write to Output in High Z  
0
20  
-
0
30  
-
0
30  
-
17 tDW  
18 tDH  
Data to Write Time Overlap 25  
Data Hold from Write Time 0  
35  
0
40  
0
-
-
-
Output Active from End of  
Write  
19 tOW  
5
-
5
-
5
-
ns  
AC TEST CONDITIONS  
TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.) unless otherwise specified.  
PARAMETER VALUE  
Input Pulse Level  
Input Rise and Fall Time  
0.8V to 2.4V  
5ns  
Input and Output Timing Reference Levels 1.5V  
70/85/100ns  
55ns  
CL = 100pF + 1TTL Load  
CL = 50pF + 1TTL Load  
Output Load  
3 of 4  
22/10/97 12:33  

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