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HY5V56DFP-P PDF预览

HY5V56DFP-P

更新时间: 2024-02-25 12:31:29
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器内存集成电路
页数 文件大小 规格书
14页 253K
描述
Synchronous DRAM, 16MX16, 6ns, CMOS, PBGA54, 8 X 13.50 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54

HY5V56DFP-P 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA54,9X9,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.24
风险等级:5.84访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PBGA-B54
JESD-609代码:e1长度:13.5 mm
内存密度:268435456 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA54,9X9,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified刷新周期:8192
座面最大高度:1.1 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:8 mm
Base Number Matches:1

HY5V56DFP-P 数据手册

 浏览型号HY5V56DFP-P的Datasheet PDF文件第8页浏览型号HY5V56DFP-P的Datasheet PDF文件第9页浏览型号HY5V56DFP-P的Datasheet PDF文件第10页浏览型号HY5V56DFP-P的Datasheet PDF文件第11页浏览型号HY5V56DFP-P的Datasheet PDF文件第12页浏览型号HY5V56DFP-P的Datasheet PDF文件第14页 
HY5V56D(L/S)FP  
COMMAND TRUTH TABLE  
DQ  
M
A10  
/AP  
Command  
Mode Register Set  
No Operation  
CKEn-1  
CKEn  
CS  
RAS  
CAS  
WE  
ADDR  
BA Note  
H
H
H
X
X
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
X
X
OP code  
X
Bank Active  
Read  
L
RA  
V
V
L
H
L
H
H
H
X
X
L
L
H
H
L
L
L
H
L
X
X
X
CA  
CA  
X
Read with Autopre-  
charge  
Write  
V
Write with Autopre-  
charge  
H
H
L
Precharge All Banks  
X
V
X
X
L
L
H
H
L
L
Precharge selected  
Bank  
Burst Stop  
DQM  
H
H
H
H
X
X
V
X
X
X
X
Auto Refresh  
H
X
L
L
L
L
L
L
H
L
Burst-Read-Single-  
WRITE  
A9 ball High  
(Other balls OP code)  
MRS  
Mode  
H
H
L
X
X
Entry  
Self  
L
H
L
L
X
H
X
H
X
H
X
V
L
X
H
X
H
X
H
X
V
H
X
H
X
H
X
H
X
V
X
Refresh1  
Exit  
L
H
L
H
L
X
X
X
H
L
Entry  
Precharge  
power  
X
X
H
L
down  
Exit  
H
H
L
Entry  
Clock  
Suspend  
H
L
L
X
X
Exit  
H
X
Note :  
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high  
2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,  
Opcode = Operand Code, NOP = No Operation  
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to  
a logic 1.  
Rev. 0.1 / Jan. 2005  
13  

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