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HY5S5A6DSFP-SE

更新时间： 2024-11-20 19:52:07
品牌 Logo 应用领域
海力士 - HYNIX 时钟动态存储器内存集成电路
页数 文件大小 规格书
25页 1064K
描述
Synchronous DRAM, 16MX16, 7ns, CMOS, PBGA54, 8 X 13.50 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54

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HY5S5A6DSFP-SE 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：TFBGA, BGA54,9X9,32
针数：54Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.24
风险等级：5.84访问模式：FOUR BANK PAGE BURST
最长访问时间：7 ns其他特性：AUTO/SELF REFRESH
最大时钟频率 (fCLK)：105 MHzI/O 类型：COMMON
交错的突发长度：1,2,4,8JESD-30 代码：R-PBGA-B54
JESD-609代码：e1长度：13.5 mm
内存密度：268435456 bit内存集成电路类型：SYNCHRONOUS DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：54
字数：16777216 words字数代码：16000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-25 °C组织：16MX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装等效代码：BGA54,9X9,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
电源：1.8 V认证状态：Not Qualified
刷新周期：8192座面最大高度：1.1 mm
自我刷新：YES连续突发长度：1,2,4,8,FP
最大待机电流：0.00035 A子类别：DRAMs
最大压摆率：0.14 mA最大供电电压 (Vsup)：1.95 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM宽度：8 mm
Base Number Matches：1

HY5S5A6DSFP-SE 数据手册

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HY5S5A6D(L/S)F(P)-xE  
4Banks x 4M x 16bits Synchronous DRAM  
DESCRIPTION  
The Hynix Mobile SDR is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular  
phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.  
The Hynix HY5S5A6D(L/S)F(P) is a 268,435,456bit CMOS Synchronous Dynamic Random Access Memory. It is organ-  
ized as 4banks of 4,194,304x16.  
The Mobile SDR provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of  
1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Mobile SDR also provides for  
special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all  
o
banks, Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in  
progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or  
Write command on any cycle(This pipelined design is not restricted by a 2N rule).  
Deep Power Down Mode is a additional operating mode for Mobile SDR. This mode can achieve maximum power re-  
duction by removing power to the memory array within each SDR. By using this feature, the system can cut off alomost  
all DRAM power without adding the cost of a power switch and giving up mother-board power-line layout flexibility.  
FEATURES  
Standard SDR Protocol  
Internal 4bank operation  
●
●
●
●
Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V  
LVCMOS compatible I/O Interface  
Low Voltage interface to reduce I/O power  
Low Power Features  
- PASR(Partial Array Self Refresh)  
- TCSR (Temperature Compensated Self Refresh)  
- DS (Drive Strength)  
- Deep Power Down Mode  
●
●
●
Programmable CAS latency of 1, 2 or 3  
-25oC ~ 85oC Operation  
Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead)  
HY5S5A6D(L/S)FP : Lead Free  
HY5S5A6D(L/S)F : Lead  
ORDERING INFORMATION  
CAS  
Latency  
Part Number  
Clock Frequency  
Organization  
Interface 54Ball FBGA  
HY5S5A6D(L/S)F-SE  
HY5S5A6D(L/S)FP-SE  
Lead  
LVCMOS  
105MHz  
3
4banks x 4Mb x 16  
Lead Free  
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for  
use of circuits described. No patent licenses are implied.  
Rev 0.4 / Feb. 2004  
1
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HY5S5B2CLFP-6E HYNIX

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