Datasheet > HY57W283220T-H

HY57W283220T-H

更新时间： 2024-11-24 19:51:59

品牌	Logo	应用领域
海力士 - HYNIX		时钟动态存储器光电二极管内存集成电路
页数	文件大小	规格书
25页	399K
描述
Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86,

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技术参数
数据手册

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HY57W283220T-H 技术参数

生命周期：	Active	包装说明：	TSSOP, TSSOP86,.46,20
Reach Compliance Code：	compliant	风险等级：	5.75
最长访问时间：	5.4 ns	最大时钟频率 (fCLK)：	133 MHz
I/O 类型：	COMMON	交错的突发长度：	1,2,4,8
JESD-30 代码：	R-PDSO-G86	内存密度：	134217728 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	32
端子数量：	86	字数：	4194304 words
字数代码：	4000000	最高工作温度：	85 °C
最低工作温度：	-25 °C	组织：	4MX32
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP86,.46,20
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	1.8/2.5,2.5 V	认证状态：	Not Qualified
刷新周期：	4096	连续突发长度：	1,2,4,8,FP
最大待机电流：	0.0006 A	子类别：	DRAMs
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
Base Number Matches：	1

HY57W283220T-H 数据手册

HY5W2A2(L/S)F / HY57W2A3220(L/S)T

HY5W22F / HY57W283220T

4Banks x 1M x 32bits Synchronous DRAM

DESCRIPTION

The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G

cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs

The Hynix HY5W2A2F series is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applica-

tions which require wide data I/O and high bandwidth. HY5W2A2F series is organized as 4banks of 1,048,576x32.

The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst

length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM

also provides for special programmable options including Partial Array Self Refresh of 1bank, 2banks, or all banks,

Temperature Compensated Self Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress

can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write

command on any cycle(This pipelined design is not restricted by a 2N rule).

Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve maximum

power reduction by removing power to the memory array within each SDRAM. By using this feature, the system can

cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board power-line lay-

out flexibility.

FEATURES

•

Standard SDRAM Protocol

Internal 4bank operation

Voltage : VDD = 2.5V, VDDQ = 1.8V & 2.5V

LVTTL compatible I/O Interface

Low Voltage interface to reduce I/O power

Low Power Features ( HY5W22F / HY57W283220T series can’t support these features)

- PASR(Partial Array Self Refresh)

- TCSR(Temperature Compensated Self Refresh)

- Deep Power Down Mode

Packages : 90ball, 0.8mm pitch FBGA / 86pin, TSOP

-25 ~ 85C Operation

•

ORDERING INFORMATION

Clock Frequency

Part No.

Organization

Interface

Package

CAS Latench

HY57W2A3220(L/S)T-H

HY5W2A2(L/S)F-H

133MHz

CL 3

4Banks x 1Mbits

x32

LVTTL

HY57W2A3220(L/S)T-8

HY5W2A2(L/S)F-8

125MHz

CL 3

4Banks x 1Mbits

x32

90balls FBGA

(HY5xxxxxxF)

86pin TSOP-II

(HY5xxxxxxT)

HY57W2A3220(L/S)T-P

HY5W2A2(L/S)F-P

100MHz

CL 2

4Banks x 1Mbits

x32

HY57W2A3220(L/S)T-S

HY5W2A2(L/S)F-S

100MHz

CL 3

4Banks x 1Mbits

x32

HY57W2A3220(L/S)T-B

HY5W2A2(L/S)F-B

66MHz

CL 2

4Banks x 1Mbits

x32

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.5/Jan. 03

12 3 4 5 6 7...25

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与HY57W283220T-H相关器件

型号	品牌	获取价格	描述	数据表
HY57W283220T-HC	HYNIX	获取价格	Synchronous DRAM, 4MX32, 5.4ns, CMOS, PDSO86,
HY57W283220T-P	HYNIX	获取价格	Synchronous DRAM, 4MX32, 7ns, CMOS, PDSO86,
HY57W283220T-SC	HYNIX	获取价格	Synchronous DRAM, 4MX32, 7ns, CMOS, PDSO86,
HY57W2A1620HCLT-B	HYNIX	获取价格	Synchronous DRAM, 8MX16, 9ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54
HY57W2A1620HCLT-BF	HYNIX	获取价格	Synchronous DRAM, 8MX16, 9ns, CMOS, PDSO54, 0.400 INCH, TSOP-54
HY57W2A1620HCLT-H	ETC	获取价格	SDRAM\|4X2MX16\|CMOS\|TSOP\|54PIN\|PLASTIC
HY57W2A1620HCLT-P	HYNIX	获取价格	Synchronous DRAM, 8MX16, 7ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54
HY57W2A1620HCLT-S	ETC	获取价格	SDRAM\|4X2MX16\|CMOS\|TSOP\|54PIN\|PLASTIC
HY57W2A1620HCLT-SF	HYNIX	获取价格	Synchronous DRAM, 8MX16, 7ns, CMOS, PDSO54, 0.400 INCH, TSOP-54
HY57W2A1620HCST-B	HYNIX	获取价格	Synchronous DRAM, 8MX16, 9ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54

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