Datasheet > 存储 > DRAM> HY57V64820HGLTP-P

HY57V64820HGLTP-P

更新时间： 2024-02-25 14:57:01

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
11页	82K
描述
4 Banks x 2M x 8Bit Synchronous DRAM

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HY57V64820HGTP

4 Banks x 2M x 8Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8.

HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read

or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V64820HGTP-5/55/6/7

HY57V64820HGTP-K

HY57V64820HGTP-H

HY57V64820HGTP-8

HY57V64820HGTP-P

HY57V64820HGTP-S

HY57V64820HGLTP-5/55/6/7

HY57V64820HGLTP-K

HY57V64820HGLTP-H

HY57V64820HGLTP-8

HY57V64820HGLTP-P

HY57V64820HGLTP-S

200/183/166/143MHz

133MHz

Normal

125MHz

100MHz

400mil 54pin TSOP II

(Pb free)

4Banks x 2Mbits x8

LVTTL

200/183/166/143MHz

133MHz

Low power

125MHz

100MHz

Note) Hynix supports lead free part for each speed grade with same specification.

This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use

of circuits described. No patent licenses are implied.

Rev. 0.1/ Nov. 03

12 3 4 5 6 7...11

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与HY57V64820HGLTP-P相关器件

型号	品牌	获取价格	描述	数据表
HY57V64820HGLTP-S	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGLT-S	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGT	ETC	获取价格	8Mx8\|3.3V\|4K\|6\|SDR SDRAM - 64M
HY57V64820HGT-5	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGT-55	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGT-6	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGT-7	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGT-8	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGT-H	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM
HY57V64820HGT-K	HYNIX	获取价格	4 Banks x 2M x 8Bit Synchronous DRAM

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