Datasheet > HY57V643220CT-I

HY57V643220CT-I

更新时间： 2024-11-26 23:57:11

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
11页	170K
描述
2Mx32\|3.3V\|4K\|5\|SDR SDRAM - 64M

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中文翻译

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HY57V643220CT-I 数据手册

HY57V643220C-I Series

4 Banks x 512K x 32Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V643220C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications

which require low power consumption and extended temperature range. HY57V643220C is organized as 4banks of

524,288x32.

HY57V643220C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

JEDEC standard 3.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 86pin TSOP-II with 0.5mm of

pin pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of

system clock

•

Data mask function by DQM0,1,2 and 3

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

Burst Read Single Write operation

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V643220CT-5I

HY57V643220CT-55I

HY57V643220CT-6I

HY57V643220CT-7I

HY57V643220CT-SI

HY57V643220CLT-5I

HY57V643220CLT-55I

HY57V643220CLT-6I

HY57V643220CLT-7I

HY57V643220CLT-SI

200MHz

183MHz

166MHz

143MHz

100MHz

200MHz

183MHz

166MHz

143MHz

100MHz

Normal

4Banksx 512Kbits

x32

LVTTL

400mil 86pin TSOP II

Low-Power

This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.5/Aug. 02

12 3 4 5 6 7...11

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与HY57V643220CT-I相关器件

型号	品牌	获取价格	描述	数据表
HY57V643220CT-P	HYNIX	获取价格	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V643220CTP-47	HYNIX	获取价格	Synchronous DRAM, 2MX32, 4.5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.5 MM PITCH, LEAD FREE,
HY57V643220CTP-55	HYNIX	获取价格	Synchronous DRAM, 2MX32, 5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.5 MM PITCH, LEAD FREE, T
HY57V643220CTP-6	HYNIX	获取价格	Synchronous DRAM, 2MX32, 5.5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.5 MM PITCH, LEAD FREE,
HY57V643220CTP-7	HYNIX	获取价格	Synchronous DRAM, 2MX32, 5.5ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.5 MM PITCH, LEAD FREE,
HY57V643220CTP-8	HYNIX	获取价格	Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.5 MM PITCH, LEAD FREE, T
HY57V643220CTP-P	HYNIX	获取价格	Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.5 MM PITCH, LEAD FREE, T
HY57V643220CTP-S	HYNIX	获取价格	Synchronous DRAM, 2MX32, 6ns, CMOS, PDSO86, 0.400 X 0.875 INCH, 0.5 MM PITCH, LEAD FREE, T
HY57V643220CT-S	HYNIX	获取价格	4 Banks x 512K x 32Bit Synchronous DRAM
HY57V643220CT-SI	ETC	获取价格	SDRAM\|4X512KX32\|CMOS\|TSSOP\|86PIN\|PLASTIC

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