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HY57U2A1620HCT-S PDF预览

HY57U2A1620HCT-S

更新时间： 2024-02-25 01:59:26
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器ISM频段光电二极管内存集成电路
页数 文件大小 规格书
24页 200K
描述
Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 INCH, TSOP2-54

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中文翻译

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HY57U2A1620HCT-S 技术参数

生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2,针数：54
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.84
访问模式：FOUR BANK PAGE BURST最长访问时间：6 ns
其他特性：AUTO/SELF REFRESHJESD-30 代码：R-PDSO-G54
JESD-609代码：e6长度：22.22 mm
内存密度：134217728 bit内存集成电路类型：SYNCHRONOUS DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：54
字数：8388608 words字数代码：8000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8MX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
认证状态：Not Qualified座面最大高度：1.2 mm
自我刷新：YES最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN BISMUTH
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL宽度：10.16 mm
Base Number Matches：1

HY57U2A1620HCT-S 数据手册

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HY5U2A6C(L)F  
4Banks x 2M x 16bits Synchronous DRAM  
DESCRIPTION  
The Hynix Low Power SDRAM is suited for non-PC application which use the batteries such as PDAs,  
2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld  
PCs.  
The Hynix HY5U2A6CF is a 134,217,728bit CMOS Synchronous Dynamic Random Access Memory. It  
is organized as 4banks of 2,097,152x16.  
The Low Power SDRAM provides for programmable options including CAS latency of 1, 2, or 3, READ  
or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave).  
And the Low Power SDRAM also provides for special programmable options including Partial Array Self  
Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks, Temperature Compensated Self  
Refresh of 15, 45, 70, or 85 degrees C. A burst of Read or Write cycles in progress can be terminated  
by a burst terminate command or can be interrupted and replaced by a new burst Read or Write com-  
mand on any cycle(This pipelined design is not restricted by a 2N rule).  
Deep Power Down Mode is a additional operating mode for Low Power SDRAM. This mode can achieve  
maximum power reduction by removing power to the memory array within each SDRAM. By using this  
feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and  
giving up mother-board power-line layout flexibility.  
FEATURES  
•
•
•
•
•
•
Standard SDRAM Protocol  
Internal 4bank operation  
Voltage : VDD = 2.5V, VDDQ = 2.5V  
LVTTL compatible I/O Interface  
Low Voltage interface to reduce I/O power  
Special Low Power Features (JEDEC standard)  
- PASR(Partial Array Self Refresh)  
- TCSR(Temperature Compensated Self Refresh)  
- Deep Power Down Mode  
•
•
CAS latency of 1, 2, or 3  
Packages : 54ball, 0.8mm pitch FBGA / 54pin, TSOP  
128M SDRAM ODERING INFORMATION  
Clock  
Frequency Latency  
CAS  
Part Number  
Organization  
Interface  
Package  
HY57U2A1620HC(L)T-H  
HY57U2A1620HC(L)T-P  
HY57U2A1620HC(L)T-S  
HY5U2A6C(L)F-H  
133MHz  
100MHz  
100MHz  
3
2
3
4banks x 2Mb x 16  
4banks x 2Mb x 16  
4banks x 2Mb x 16  
4banks x 2Mb x 16  
4banks x 2Mb x 16  
4banks x 2Mb x 16  
54pin TSOP-II  
54pin TSOP-II  
54pin TSOP-II  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
133MHz  
100MHz  
100MHz  
3
2
3
54ball FBGA  
54ball FBGA  
54ball FBGA  
HY5U2A6C(L)F-P  
HY5U2A6C(L)F-S  
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for  
use of circuits described. No patent licenses are implied.  
Rev. 0.9 / Oct. 01  
1234567...24

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