HY29LV160TF-12E PDF预览

HY29LV160TF-12E

更新时间: 2025-07-28 13:00:27
品牌 Logo 应用领域
海力士 - HYNIX 闪存存储内存集成电路
页数 文件大小 规格书
48页 516K
描述
Flash, 1MX16, 120ns, PBGA48, 8 X 9 MM, FBGA-48

HY29LV160TF-12E 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:8 X 9 MM, FBGA-48针数:48
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.51风险等级:5.66
Is Samacsys:N最长访问时间:120 ns
备用内存宽度:8启动块:TOP
JESD-30 代码:R-PBGA-B48JESD-609代码:e1
长度:9 mm内存密度:16777216 bit
内存集成电路类型:FLASH内存宽度:16
功能数量:1端子数量:48
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:1MX16
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行:PARALLEL编程电压:2.7 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
类型:NOR TYPE宽度:8 mm
Base Number Matches:1

HY29LV160TF-12E 数据手册

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HY29LV160  
16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory  
KEY FEATURES  
n Single Power Supply Operation  
n 100,000 Write Cycles per Sector Minimum  
– Read, program and erase operations from  
2.7 to 3.6 volts  
– Ideal for battery-powered applications  
n High Performance  
n Data# Polling and Toggle Bits  
Provide software confirmation of  
completion of program and erase  
operations  
– 70, 80, 90 and 120 ns access time  
versions  
n Ultra-low Power Consumption (Typical  
Values At 5 Mhz)  
n Ready/Busy# Pin  
Provides hardware confirmation of  
completion of program and erase  
operations  
– Automatic sleep mode current: 1 µA  
– Standby mode current: 1 µA  
– Read current: 9 mA  
n Hardware Reset Pin (RESET#) Resets the  
Device to Reading Array Data  
n Compliant With Common Flash Memory  
Interface (CFI) Specification  
– Program/erase current: 20 mA  
n Flexible Sector Architecture:  
– One 16 KB, two 8 KB, one 32 KB and  
thirty-one 64 KB sectors in byte mode  
– One 8 KW, two 4 KW, one 16 KW and  
thirty-one 32 KW sectors in word mode  
– Top or bottom boot block configurations  
available  
Flash device parameters stored directly  
on the device  
Allows software driver to identify and use  
a variety of different current and future  
Flash products  
n Compatible With JEDEC standards  
Pinout and software compatible with  
single-power supply Flash devices  
Superior inadvertent write protection  
n Space Efficient Packaging  
48-pin TSOP and 48-ball FBGA packages  
n Sector Protection  
– Allows locking of a sector or sectors to  
prevent program or erase operations  
within that sector  
– Sectors lockable in-system or via  
programming equipment  
– Temporary Sector Unprotect allows  
changes in locked sectors (requires high  
voltage on RESET# pin)  
LOGIC DIAGRAM  
n Fast Program and Erase Times  
– Sector erase time: 0.25 sec typical for  
each sector  
20  
8
7
– Chip erase time: 8 sec typical  
– Byte program time: 9 µs typical  
n Unlock Bypass Program Command  
– Reduces programming time when issuing  
multiple program command sequences  
n Automatic Erase Algorithm Preprograms  
and Erases Any Combination of Sectors  
or the Entire Chip  
n Erase Suspend/Erase Resume  
– Suspends an erase operation to allow  
reading data from, or programming data  
to, a sector that is not being erased  
– Erase Resume can then be invoked to  
complete suspended erasure  
A[19:0]  
CE#  
DQ[7:0]  
DQ[14:8]  
OE#  
DQ15/A-1  
RY/BY#  
W E #  
RESET#  
BYTE#  
n Automatic Program Algorithm Writes and  
Verifies Data at Specified Addresses  
Preliminary  
Revision 1.2, May 2001  

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