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HY27SF161G2M-SPEB PDF预览

HY27SF161G2M-SPEB

更新时间: 2024-11-06 19:04:35
品牌 Logo 应用领域
海力士 - HYNIX 光电二极管内存集成电路
页数 文件大小 规格书
48页 424K
描述
Flash, 64MX16, 30ns, PDSO48, 12 X 17 MM, 0.65 MM HEIGHT, LEAD FREE, USOP1-48

HY27SF161G2M-SPEB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:VSSOP, TSSOP48,.71,20针数:48
Reach Compliance Code:compliantECCN代码:3A991.B.1.A
HTS代码:8542.32.00.51风险等级:5.84
最长访问时间:30 ns命令用户界面:YES
数据轮询:NOJESD-30 代码:R-PDSO-G48
长度:15.4 mm内存密度:1073741824 bit
内存集成电路类型:FLASH内存宽度:16
功能数量:1部门数/规模:1K
端子数量:48字数:67108864 words
字数代码:64000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-25 °C
组织:64MX16封装主体材料:PLASTIC/EPOXY
封装代码:VSSOP封装等效代码:TSSOP48,.71,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
页面大小:1K words并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:1.8 V
编程电压:1.8 V认证状态:Not Qualified
就绪/忙碌:YES座面最大高度:0.65 mm
部门规模:64K最大待机电流:0.00005 A
子类别:Flash Memories最大压摆率:0.015 mA
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
切换位:NO类型:NAND TYPE
宽度:12 mmBase Number Matches:1

HY27SF161G2M-SPEB 数据手册

 浏览型号HY27SF161G2M-SPEB的Datasheet PDF文件第2页浏览型号HY27SF161G2M-SPEB的Datasheet PDF文件第3页浏览型号HY27SF161G2M-SPEB的Datasheet PDF文件第4页浏览型号HY27SF161G2M-SPEB的Datasheet PDF文件第5页浏览型号HY27SF161G2M-SPEB的Datasheet PDF文件第6页浏览型号HY27SF161G2M-SPEB的Datasheet PDF文件第7页 
HY27UF(08/16)1G2M Series  
HY27SF(08/16)1G2M Series  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash  
Document Title  
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory  
Revision History  
Revision  
History  
No.  
Draft Date Remark  
0.0  
1) Initial Draft.  
Aug. 2004  
Preliminary  
1) Correct Fig.10 Sequential out cycle after read  
2) Add the text to Fig.1, Table.1, Table.2  
- text : IO15 - IO8 (x16 only)  
3) Delete ‘3.2 Page program NOTE 1.  
- Note : if possible it is better to remove this constrain  
4) Change the text ( page 10,13, 45)  
0.1  
Sep. 2004  
Preliminary  
- 2.2 Address Input : 28 Addresses -> 27 Addresses  
- 3.7 Reset : Fig.29 -> Fig.30  
- 5.1 Automatic page read after power up : Fig.30 -> Fig.29  
5) Add 5.3 Addressing for program operation & Fig.34  
1) Change TSOP, WSOP, FBGA package dimension & figures.  
- Change TSOP, WSOP, FBGA package mechanical data  
- Change FBGA thickness (1.2 -> 1.0 mm)  
2) Correct TSOP, WSOP Pin configurations.  
- 38th NC pin has been changed Lockpre(figure 3,4)  
3) Edit figure 15,19 & table 4  
0.2  
Oct. 2004  
Preliminary  
4) Add Bad Block Management  
5) Change Device Identifier 3rd Byte  
- 3rd Byte ID is changed. (reserved -> don't care)  
- 3rd Byte ID table is deleted.  
1) Add Errata  
tCLS tCLH tWP tALS tALH tDS  
tWC  
50  
tR  
25  
27  
Specification  
Relaxed value  
0
5
10  
15  
25  
40  
0
5
10  
15  
20  
25  
60  
2) LOCKPRE is changed to PRE.  
- Texts, Table, Figures are changed.  
3) Add Note.4 (table.14)  
0.3  
Nov.29 2004 Preliminary  
4) Block Lock Mechanism is deleted.  
- Texts, Table, figures are deleted.  
5) Add Application Note(Power-On/Off Sequence & Auto Sleep mode.)  
- Texts & Figures are added.  
6) Edit the figures. (#10~25)  
1) Change AC characteristics(tREH)  
before: 20ns -> after: 30ns  
0.4  
2) Edit Note.1 (page. 21)  
Jan.19 2005 Preliminary  
3) Edit the Application note 1,2  
4) Edit The Address cycle map (x8, x16)  
Rev 1.1 / Nov. 2005  
1

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