Datasheet > HSD4M64B4-F8

HSD4M64B4-F8

更新时间： 2024-09-24 03:01:19

品牌	Logo	应用领域
HANBIT		动态存储器
页数	文件大小	规格书
11页	87K
描述
Synchronous DRAM Module 32Mbyte (4Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V

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HSD4M64B4-F8 数据手册

HANBit

HSD4M64B4

Synchronous DRAM Module 32Mbyte (4Mx64-Bit), SO-DIMM,

4Banks, 4K Ref., 3.3V

Part No. HSD4M64B4

GENERAL DESCRIPTION

The HSD4M64B4 is a 4M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of

four CMOS 1M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy substrate.

Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD4M64B4

is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge connector

sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on

every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a

variety of high bandwidth, high performance memory system applications All module components may be powered from a

single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

• Part Identification

HSD4M64B4-F/10 :100MHz ( CL=2)

HSD4M64B4-F/10L :100MHz ( CL=3)

HSD4M64B4-F/12 :125MHz ( CL=3)

HSD4M64B4-F/13 :133Mhz (CL=3)

* F : Auto Self-Refresh with Low Power

• Burst mode operation

• Auto & self refresh capability (4096 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• MRS cycle with address key programs

- Latency (Access from column address)

- Burst length (1, 2, 4, 8 & Full page)

- Data scramble (Sequential & Interleave)

• JEDEC standard

• All inputs are sampled at the positive going edge of the system clock

• The used device is 1Mx16Bitx4Banks SDRAM

URL:www.hbe.co.kr

HANBit Electronics Co.,Ltd.

REV.1.0(August.2002)

- 1 -

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