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HSD64M64F8K-10L PDF预览

HSD64M64F8K-10L

更新时间: 2024-02-10 07:28:15
品牌 Logo 应用领域
HANBIT 动态存储器
页数 文件大小 规格书
12页 204K
描述
Synchronous DRAM Module 512Mbyte (64Mx64bit), SMM, based on 32Mx8, 4Banks, 4K Ref., 3.3V

HSD64M64F8K-10L 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

HSD64M64F8K-10L 数据手册

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HANBit  
HSD64M64F8K  
Synchronous DRAM Module 512Mbyte (64Mx64bit), SMM, based on  
32Mx8, 4Banks, 4K Ref., 3.3V  
Part No. HSD64M64F8K  
GENERAL DESCRIPTION  
The HSD64M64F8K is a 64M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists  
of sixteen CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin  
TSSOP package on a 120-pin glass-epoxy. One 0.22uF and two 0.0022uF decoupling capacitors are mounted on the  
printed circuit board in parallel for each SDRAM. The HSD64M64F8k is a SMM(Stackable Memory Module  
type) .Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on  
every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a  
variety of high bandwidth, high performance memory system applications All module components may be powered from a  
single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.  
FEATURES  
Part Identification  
HSD64M64F8K : 100MHz (CL=2)  
Burst mode operation  
Auto & self refresh capability (4096 Cycles/64ms)  
LVTTL compatible inputs and outputs  
Single 3.3V ±0.3V power supply  
MRS cycle with address key programs  
- Latency (Access from column address)  
- Burst length (1, 2, 4, 8 & Full page)  
- Data scramble (Sequential & Interleave)  
All inputs are sampled at the positive going edge of the system clock  
The used device is 8M x 8bit x 4Banks SDRAM  
URL:www.hbe.co.kr  
REV.1.0 (August.2002)  
- 1 -  
HANBit Electronics Co.,Ltd.  

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