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HSD16M64B4W-13 PDF预览

HSD16M64B4W-13

更新时间: 2024-11-12 03:20:43
品牌 Logo 应用领域
HANBIT 动态存储器
页数 文件大小 规格书
10页 106K
描述
Synchronous DRAM Module 128Mbyte(16Mx64-Bit), 144pin SO-DIMM, 4Banks, 8K Ref., 3.3V

HSD16M64B4W-13 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.84

HSD16M64B4W-13 数据手册

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HANBit  
HSD16M64B4W  
Synchronous DRAM Module 128Mbyte(16Mx64-Bit), 144pin SO-DIMM,  
4Banks, 8K Ref., 3.3V  
Part No.  
GENERAL DESCRIPTION  
The HSD16M64B4W is a 16M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists  
of four CMOS 2M x 16 bit x 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 144-pin glass-epoxy substrate.  
Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The  
HSD16M64B4W is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin  
edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions  
are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be  
useful for a variety of high bandwidth, high performance memory system applications All module components may be  
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.  
FEATURES  
Part Identification  
HSD16M64B4W-10 : 100MHz (CL=2)  
HSD16M64B4W-10L : 100MHz (CL=3)  
HSD16M64B4W-12 : 125MHz (CL=3)  
HSD16M64B4W-13 : 133MHz (CL=3)  
Burst mode operation  
Auto & self refresh capability (8192 Cycles/64ms)  
LVTTL compatible inputs and outputs  
Single 3.3V ±0.3V power supply  
MRS cycle with address key programs  
- Latency (Access from column address)  
- Burst length (1, 2, 4, 8 & Full page)  
- Data scramble (Sequential & Interleave)  
All inputs are sampled at the positive going edge of the system clock  
The used device is 4M x 16bit x 4Banks SDRAM  
URL: www.hbe.co.kr  
REV 1.0 (August.2002)  
1
HANBit Electronics Co.,Ltd.  

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