SPECIFICATIONS (continued)
(TA=25°C; VDD =+15V, VREF = +10V; IO1 = IO2 = GND = 0V; unipolar unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNIT
CONDITIONS
DIGITAL INPUTS
Logic Levels
VIH
2.4
VDD
2.4
0.8
0.8
±1.0
±10
Volts
Volts
Volts
Volts
µA
Note 5
VIL
-0.3
Note 5
Input Current
VIN = 0V or VDD
Note 5 and 15
VIN = 0; Note 5 and 14
Note 5
µA
Input Capacitance
Bits 1—12
Coding
8
pF
Unipolar
Binary
Bipolar
Offset Binary
POWER REQUIREMENTS
Voltage Range
+5
+15
+16
2.5
Volts
Volts
mA
Note 16
Note 5
Supply Current
2.0
0.2
All digital inputs VIL or VIH
Note 5; all digital inputs VIL or
VIH
All digital inputs 0V or 5V to
VDD
2.5
mA
0.5
1.0
mA
mA
Note 5; all digital inputs 0V or
5V to VDD
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
-AK, -AJ
-AB, -AA
Storage Temperature
Package
0
-40
-65
+70
+85
+150
°C
°C
°C
-AK, -AJ
18-pin plastic DIP, 20-pin PLCC, 18–pin SOIC
Notes and Cautions:
1.
2.
Do not apply voltages higher than VDD or less than GND potential on any terminal other than VREF or V
.
The digital inputs are diode-clamp protected against ESD damage. However, permanent damage mayRoFcBcur
on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until
ready to use.
3.
4.
Use proper anti-static handling procedures.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation at or above these specifications is not implied.
Exposure to the above maximum rated conditions for extended periods may affect device reliability.
5.
6.
From T to TMAX.
IntegralMNINon-linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive
deviation and the greatest negative deviation from the theoretical value of any given input combination.
Differential Non-linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
7.
8.
9.
AC performance characteristics are included for design guidance only and are subject to sample testing only.
RL = 100Ω, CEXT = 13pF; all data inputs 0V to VDD or VDD to 0V; from 50% digital input change to 90% of final
analog output.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Settling to ±0.01% FSR (strobed); all data inputs 0V to VDD or VDD to 0V.
VREF = 0V, DAC register alternatively loaded with all 0’s and all 1’s.
VREF = 20VP-P; F = 10kHz sinewave.
VREF = 20VP-P; F = 1kHz sinewave.
Guaranteed by design, but not production tested.
Logic inputs are MOS gates. I typically is less than 1nA @ 25°C.
Accuracy is guaranteed at VDDIN= +15V only.
Measured using internal feedback resistor with DAC loaded with all 1’s.
All digital inputs = 0V.
HS7541A
12-Bit CMOS Multiplying DAC
© Copyright 2000 Sipex Corporation
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