5秒后页面跳转
捷配首页

Datasheet > HPA00021DGGR
HPA00021DGGR PDF预览

HPA00021DGGR

更新时间： 2024-11-11 21:55:31
品牌 Logo 应用领域
德州仪器 - TI 输出元件输入元件
页数 文件大小 规格书
9页 154K
描述
14-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS

阅读下载

中文翻译

获取价格

HPA00021DGGR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：,Reach Compliance Code：compliant
风险等级：5.84JESD-609代码：e4
逻辑集成电路类型：D FLIP-FLOP湿度敏感等级：2
峰值回流温度（摄氏度）：260端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

HPA00021DGGR 数据手册

 浏览型号HPA00021DGGR的Datasheet PDF文件第2页浏览型号HPA00021DGGR的Datasheet PDF文件第3页浏览型号HPA00021DGGR的Datasheet PDF文件第4页浏览型号HPA00021DGGR的Datasheet PDF文件第5页浏览型号HPA00021DGGR的Datasheet PDF文件第6页浏览型号HPA00021DGGR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢀꢀ ꢄꢅ ꢆꢇ ꢈꢉ ꢂ  
ꢆ ꢃ ꢊꢋꢌ ꢄ ꢍꢎ ꢏꢌ ꢀꢄ ꢎꢍꢎꢐ ꢋ ꢑꢒ ꢒꢎ ꢍ  
ꢓ ꢌꢄ ꢔ ꢀꢀ ꢄꢕ ꢖ ꢗ ꢌꢁ ꢘꢑꢄ ꢀ ꢙꢁꢐ ꢚ ꢑꢄ ꢘꢑ ꢄꢀ  
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002  
DGG PACKAGE  
(TOP VIEW)  
D
Member of the Texas Instruments  
Widebus Family  
D
Supports SSTL_2 Data Inputs  
Q1  
Q2  
GND  
D1  
D2  
GND  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
D
Outputs Meet SSTL_2 Class II  
Specifications  
D
D
D
Differential Clock (CLK and CLK) Inputs  
V
V
DDQ  
Q3  
CC  
D3  
D4  
D5  
D6  
D7  
Supports LVCMOS Switching Levels on the  
RESET Input  
Q4  
Q5  
GND  
RESET Input Disables Differential Input  
Receivers, Resets All Registers, and  
Forces All Outputs Low  
V
DDQ  
Q6 10  
39 CLK  
D
D
D
Flow-Through Architecture Optimizes PCB  
Layout  
Q7  
CLK  
11  
12  
38  
37  
V
V
DDQ  
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
GND 13  
Q8 14  
Q9 15  
36 GND  
35  
V
REF  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
34 RESET  
V
16  
33 D8  
DDQ  
GND 17  
Q10 18  
Q11 19  
Q12 20  
32 D9  
– 1000-V Charged-Device Model (C101)  
31 D10  
30 D11  
29 D12  
description  
V
21  
28  
V
DDQ  
CC  
This 14-bit registered buffer is designed for 2.3-V  
to 2.7-V V operation.  
GND 22  
Q13 23  
Q14 24  
27 GND  
26 D13  
25 D14  
CC  
All inputs are SSTL_2, except the LVCMOS reset  
(RESET) input. All outputs are SSTL_2, Class II  
compatible.  
The SN74SSTV16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing  
of CLK going high and CLK going low.  
The device supports low-power standby operation. When RESET is low, the differential input receivers are  
disabled and undriven (floating) data, clock, and reference voltage (V  
) inputs are allowed. In addition, when  
REF  
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must  
be held at a valid logic high or low level.  
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in  
the low state during power up.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
0°C to 70°C  
TSSOP – DGG Tape and reel SN74SSTV16857DGGR  
SSTV16857  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
ꢘ
ꢘ
ꢍ
ꢚ
ꢫ
ꢐ
ꢦ
ꢑ
ꢛ
ꢤ
ꢄ
ꢥ
ꢌ
ꢟ
ꢚ
ꢝ
ꢁ
ꢞ
ꢐ
ꢙ
ꢄ
ꢙ
ꢜ
ꢝ
ꢧ
ꢞ
ꢟ
ꢥ
ꢠ
ꢡ
ꢢ
ꢢ
ꢣ
ꢣ
ꢜ
ꢜ
ꢟ
ꢟ
ꢝ
ꢝ
ꢜ
ꢤ
ꢤ
ꢨ
ꢥ
ꢦ
ꢠ
ꢠ
ꢧ
ꢧ
ꢝ
ꢣ
ꢢ
ꢡ
ꢤ
ꢤ
ꢟ
ꢞ
ꢨ
ꢄꢧ  
ꢦ
ꢩ
ꢤ
ꢪ
ꢜ
ꢥ
ꢢ
ꢤ
ꢣ
ꢜ
ꢣ
ꢟ
ꢠ
ꢝ
ꢦ
ꢫ
ꢢ
ꢝ
ꢣ
ꢣ
ꢧ
ꢤ
ꢬ
ꢠ
ꢟ
ꢥ
ꢣ
ꢟ
ꢠ
ꢡ
ꢣ
ꢟ
ꢤ
ꢨ
ꢜ
ꢞ
ꢜ
ꢥ
ꢧ
ꢠ
ꢣ
ꢭ
ꢣ
ꢧ
ꢠ
ꢟ
ꢞ
ꢮ
ꢢ
ꢌ
ꢝ
ꢡ
ꢧ
ꢤ
ꢣ
ꢢ
ꢝ
ꢫ
ꢢ
ꢠ
ꢫ
ꢯ
ꢢ
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
ꢠ
ꢠ
ꢢ
ꢝ
ꢣ
ꢰ
ꢬ
ꢘ
ꢠ
ꢟ
ꢫ
ꢦ
ꢥ
ꢣ
ꢜ
ꢟ
ꢝ
ꢨ
ꢠ
ꢟ
ꢥ
ꢧ
ꢤ
ꢤ
ꢜ
ꢝ
ꢱ
ꢫ
ꢟ
ꢧ
ꢤ
ꢝ
ꢟ
ꢣ
ꢝ
ꢧ
ꢥ
ꢧ
ꢤ
ꢤ
ꢢ
ꢠ
ꢜ
ꢪ
ꢰ
ꢜ
ꢝ
ꢥ
ꢪ
ꢦ
ꢫ
ꢧ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

与HPA00021DGGR相关器件

型号 品牌 获取价格 描述 数据表
HPA00033DTR TI

获取价格

 		Single Ended Active Clamp/Reset PWM
HPA00034DTR TI

获取价格

 		Single Ended Active Clamp/Reset PWM
HPA00035DTR TI

获取价格

 		Single Ended Active Clamp/Reset PWM
HPA00036DTR TI

获取价格

 		Single Ended Active Clamp/Reset PWM
HPA00086DDCR TI

获取价格

 		HPA00086DDCR
HPA00138RHLR TI

获取价格

 		4.5A BATTERY CHARGE CONTROLLER, 1100kHz SWITCHING FREQ-MAX, PQCC20, 3.50 X 4.50 MM, GREEN,
HPA00420RGVR TI

获取价格

 		2.4-GHz RF Front End
HPA00530RGER TI

获取价格

 		IC,SMPS CONTROLLER,VOLTAGE-MODE,LLCC,24PIN,PLASTIC
HPA00531DBVR TI

获取价格

 		1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5, GREEN, PLASTIC, SOT-23, 5 PIN
HPA00706DTR-2 TI

获取价格

 		Single Ended Active Clamp/Reset PWM

与HPA00021DGGR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证