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HMC895LP4ETR PDF预览

HMC895LP4ETR

更新时间: 2024-11-09 14:51:07
品牌 Logo 应用领域
亚德诺 - ADI LTE输入元件
页数 文件大小 规格书
8页 1462K
描述
Filter - Tunable, Band Pass SMT, 6.8 - 12.6

HMC895LP4ETR 数据手册

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HMC895LP4E  
v01.0911  
FILTER - TUNABLE, BAND PASS SMT  
6.8 - 12.6 GHz  
Typical Applications  
The HMC895LP4E is ideal for:  
Features  
Fast Tuning Response  
Excellent Wideband Rejection  
• Test & Measurement Equipment  
• Military RADAR & EW/ECM  
• SATCOM & Space  
Tunable low side/high side rejection “notch”  
Single Chip Replacement  
for Mechanically Tuned Designs  
• Industrial & Medical Equipment  
Functional Diagram  
24 Lead 4x4 mm SMT Packag
General Descriptio
The HMC895LP4E is MMInd pasfilter which  
features a user setable passnd equency. The  
3 dB filter banidtapproximaely 10%. The 20  
dB filter bandwidth is apoximately 22%. The center  
frequenccan be varied etween 6.8 and 12.6  
GHz applyan analog tune voltage between 0  
and 14Ts tunablfilter can be used as a much  
smaller alnativo physically large switched filter  
banks and catuned filters. The HMC895LP4E has  
excellent microphonics due to the monolithic design,  
proes a dynamically adjustable solution in  
adved communications applications.  
Electrical Specifications, = +°Vfctl = Vnctl Unless Otherwise Stated  
ameter  
Min.  
6.8  
Typ.  
Max.  
12.6  
Units  
GHz  
%
Fcenter Tuning Range  
3 dB Bandwidth  
10  
Low Side Rejection Frequency (
High Side Rejection cy (RejB)  
Low Side Sub-n (Rejn >40 dB)  
High Side Sub(Rejection >40 dB)  
Re-entry FrequdB)  
Insertion Loss  
0.88 *Fcenter  
GHz  
GHz  
GHz  
GHz  
GHz  
dB  
1.10 *Fcenter  
0.75 *Fcenter  
1.22 *Fcenter  
>40  
9
Return Loss (2 dB bandwidth)  
12  
28  
8
dB  
Input IP3 (Pin = 0 to +15 dBm)  
dBm  
dBm  
dBm  
V
Input Power @ 5° Shift In Insertion Phase (Vfctl = 0V)  
Input Power @ 5° Shift In Insertion Phase (Vfctl = 1V)  
Frequency Control Voltage (Vfctl)  
16.5  
0
0
14  
1
Source/Sink Current (Ifctl  
mA  
Low Side/High Side Rejection Control Voltage (Vnctl)  
Source/Sink current (Inctl)  
14  
1
V
mA  
Residual Phase Noise [1] (100 kHz Offset)  
-155  
-1.0  
dBc/Hz  
MHz/°C  
ns  
Fcenter Drift Rate  
Tuning Speed, Phase Settling to within 10° [2]  
<200  
[1] Optimum residual phase noise performance requires the use of a low noise driver circuit.  
[2] Tuning speed includes 40 ns tuning voltage ramp from driver.  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
For price, delivery, and to place orders: Analog Devices, Inc.,  
responsibilityisassumedby AnalogDevicesfor itsuse, norforanyinfringementsofpatentsor other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
Phone: 781-329-4700 • Order online at www.analog.com  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are thepropertyoftheir respectiveowners.
1
Application Support: Phone: 1-800-ANALOG-D  

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