Output Enable Timing Diagram
OE
Bit 1 – Bit 12
TDLZ
TDHZ
TDZL
TDZH
Switching Specifications
(AVDD = +5V, DRVDD = +5V)
Parameter
Symbol
Min
50
23
23
3
Typ
Max
Units
ns
Clock Period (1)
tC
Clock Pulsewidth High (46% of tC) (1)
Clock Pulsewidth Low (46% of tC) (1)
Output Delay
tCH
tCL
tOD
ns
ns
25
ns
High Z to Output High (DRVDD=5V) (2)
High Z to Output Low (DRVDD=5V) (2)
Output High to High Z (DRVDD=5V) (2)
Output Low to High Z (DRVDD=5V) (2)
High Z to Output High (DRVDD=3.3V) (2)
High Z to Output Low (DRVDD=3.3V) (2)
Output High to High Z (DRVDD=3.3V) (2)
Output Low to High Z (DRVDD=3.3V) (2)
TDZH_50
TDZL_50
TDHZ_50
TDLZ_50
TDZH_33
TDZL_33
TDHZ_33
TDLZ_33
25
25
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
(1) These are parameters of the input clock signal to the chip.
(2) Refer to “Output Enable Timing Diagram” for waveform.
Radiation Specifications
Parameter
Limit
Units
Total Dose Hardness
Single Event Latchup (1)
Soft Error Rate
5 x 105
rad(Si)
MeV-cm2/mg
120
See note (2)
1 x 1012
Dose Rate Survivability
rad(Si)/s
N/cm2
Neutron (3)
1 x 1013
(1) The SOI CMOS technology is immune to latchup.
(2) In a particle radiation environment, output code errors may occasionally occur. These
are temporary and normal operation will resume on subsequent clock cycles.
(3) 1MeV equivalent energy, Unbiased.