Datasheet > HMADC9225NZG

HMADC9225NZG

更新时间： 2024-01-26 13:56:09

品牌	Logo	应用领域
霍尼韦尔 - HONEYWELL		转换器
页数	文件大小	规格书
11页	4897K
描述
ADC, Proprietary Method

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技术参数
数据手册

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HMADC9225NZG 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.65	转换器类型：	ADC, PROPRIETARY METHOD
输出位码：	OFFSET BINARY	Base Number Matches：	1

HMADC9225NZG 数据手册

Simplified Functional Block Diagram

DRVDD

DRVSS

REFP, REFN

VINP

MDAC1

S/H

MDAC2

MDAC3

X16

VINN

Correct

Logic

Data

Output

Drivers

Bit 1 – Bit 12

A/D

Clock In

Clock

Output

Tri-State

Control

Buffer

Master Bias

IREF

Output

Enable

REFT

Diff

Buffer

CML

Gen

REFB

–

AVDD

AVSS

RBIAS

VREF

REFCOM

* = 0.1uF in parallel

with a 10uF

External

Reference

Input

5kΩ

Cap*

0.1uF

CLK

0.1uF

Pin Description

DRVDD 28

DRVSS 27

AVDD 26

AVSS 25

VIN B 24

VIN A 23

CML 22

Pin Name

CLK

Description

Clock Input

BIT 12 (LSB)

BIT 11

BIT 10

BIT 9

BIT 12

BIT 11 – 2

BIT 1

Least Signiﬁcant Data Bit (LSB)

Data Output Bit

3-12

Most Signiﬁcant Bit (MSB)

Output Enable (high active)

+5V Analog Supply

AVDD

AVSS

Analog Ground

BIT 8

RBIAS

VREF INPUT

REFCOMM

REFB

Reference Current Bias Resistor

Reference Voltage Input

Reference Common

Noise Reduction Pin

Common Mode Level (AVDD/2)

Analog Input (+)

BIT 7

BIT 6

REFT 21

BIT 5

REFB

REFCOM

VREF IN

RBIAS

REFT

BIT 4

CML

VINA

BIT 3

VINB

Analog Input (-)

BIT 2

AVSS

Analog Ground

AVDD

+5V Analog Supply

BIT 1 (MSB)

AVSS

DRVSS

DRDVDD

Digital Output Driver Ground

AVDD

+5V or 3.3V Digital Output Driver Supply

123 4 5 6 7...11

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