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HMADC9225NZG

更新时间： 2024-01-09 11:05:49
品牌 Logo 应用领域
霍尼韦尔 - HONEYWELL 转换器
页数 文件大小 规格书
11页 4897K
描述
ADC, Proprietary Method

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HMADC9225NZG 技术参数

生命周期：Active包装说明：,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65转换器类型：ADC, PROPRIETARY METHOD
输出位码：OFFSET BINARYBase Number Matches：1

HMADC9225NZG 数据手册

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Digital Specifications  
(AVDD = +5V, DRVDD = +5V, unless otherwise noted)  
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
Logic Inputs (CLK, OE)  
High Level Input Voltage (DRVDD = +5V)  
High Level Input Voltage (DRVDD =+3.3V)  
Low Level Input Voltage (DRVDD = +5V)  
Low Level Input Voltage (DRVDD = +3.3V)  
High Level Input Current (DRVDD=5V, VIN=5V)  
Low Level Input Current (DRVDD=5V, VIN=0V)  
High Level Input Current (DRVDD=3.3V, VIN=3.3V)  
Low Level Input Current (DRVDD=3.3V, VIN=0V)  
Input Capacitance (1)  
VIH_50  
VIH_33  
VIL_50  
VIL_33  
IIH_50  
IIL_50  
IIH_33  
IIL_33  
CIN  
3.5  
2.3  
V
V
1.0  
1.0  
10  
10  
10  
10  
V
V
-10  
-10  
-10  
-10  
µA  
µA  
µA  
µA  
pF  
5
Logic Outputs (D1-D12 with DRVDD = +5V)  
High Level Output Voltage(IOH = -50µA)  
High Level Output Voltage(IOH = -0.5mA)  
Low Level Output Voltage(IOL = 1.6mA)  
Low Level Output Voltage(IOL = 50µA)  
VOH1_50  
VOH2_50  
VOL2_50  
VOL1_50  
IOZH_50  
IOZL_50  
4.5  
2.4  
V
V
0.4  
0.1  
10  
V
V
High Z Output Current (DRVDD=5V, OE=0V, VOUT=5V)  
High Z Output Current (DRVDD=5V, OE=0v, VOUT=0V)  
Logic Outputs (D1-D12 with DRVDD = +3.3V)  
High Level Output Voltage(IOH = -50µA)  
High Level Output Voltage(IOH = -0.5mA)  
Low Level Output Voltage(IOL = 50µA)  
-10  
-10  
µA  
µA  
10  
VOH1_33  
VOH2_33  
VOL1_33  
VOL2_33  
IOZH_33  
IOZL_33  
COUT  
2.95  
2.80  
V
V
0.05  
0.4  
10  
V
Low Level Output Voltage(IOL = 1.6mA)  
High Z Output Current (DRVDD=3.3V, VOE=0V, VOUT=3.3V)  
High Z Output Current (DRVDD=3.3V, VOE=0V, VOUT=0V)  
Output Capacitance (1)  
V
-10  
-10  
µA  
µA  
pF  
10  
5
(1) Guaranteed but not tested.  
Gain Error  
Definitions of Specifications  
The first code transition should occur at an analog value 1/2 LSB  
above negative full scale. The last transition should occur at an analog  
value 1 1/2 LSB below the nominal full scale.  
Integral Nonlinearity (INL)  
INL refers to the deviation of each individual code from a line drawn  
from “negative full scale” through “positive full scale.” The point used  
as “negative full scale” occurs 1/2 LSB before the first code transition.  
“Positive full scale” is defined as a level 1 1/2 LSB beyond the last  
code transition. The deviation is measured from the middle of each  
particular code to the true straight line.  
Gain error is the deviation of the actual difference between first and  
last code transitions and the ideal difference between first and last  
code transitions.  
Temperature Drift  
The temperature drift for zero error and gain error specifies the maximum  
change from the initial (+25°C) value to the value at -55°C or +125°C.  
Differential Nonlinearity (DNL, No Missing Codes)  
An ideal ADC exhibits code transitions that are exactly 1 LSB apart.  
DNL is the deviation from this ideal value. Guaranteed no missing  
codes to 12-bit resolution indicate that all 4096 codes, respectively,  
must be present over all operating ranges.  
Aperture Jitter  
Aperture jitter is the variation in aperture delay for successive samples  
and is manifested as noise on the input to the A/D.  
Aperture Delay  
Zero Error  
Aperture delay is a measure of the sample-and-hold amplifier (SHA)  
performance and is measured from the rising edge of the clock input  
to when the input signal is held for conversion.  
The major carry transition should occur for an analog value 1/2 LSB  
below VINA = VINB. Zero error is defined as the deviation of the  
actual transition from that point.  
1...4567891011

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