Pin Descriptions
Pin Name
Description
Pin Name
Description
A0-A171
BA0, BA1
BG0, BG1
I2C serial bus clock for SPD-TSE
I2C serial bus line for SPD-TSE
I2C slave address select for SPD-TSE
SDRAM parity input
SDRAM address bus
SDRAM bank select
SCL
SDA
SDRAM bank group select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
SA0-SA2
PARITY
VDD
RAS_n2
CAS_n3
WE_n4
SDRAM I/OO and core power supply
Chip ID lines
C0, C1, C2
Optional power Supply on socket but
not used on UDIMM
CS0_n, CS1_n, DIMM Rank Select Lines
12V
VREFCA
VSS
SDRAM command/address reference
supply
CKE0, CEK1
ODT0, ODT1
SDRAM clock enable lines input
SDRAM on-die termination control lines
input
Power supply return (ground)
ACT_n
DQ0-DQ63
CB0-CB7
SDRAM activate
VDDSPD
ALERT_n
VPP
Serial SPD-TSE positive power supply
SDRAM ALERT_n output
SDRAM Supply
DIMM memory data bus
DIMM ECC check bits
Dummy loads for mixed populations of
x4 based and x8 based RDIMMs.
TDQS0_t-TDQS8_t
TDQS0_c-TDQS8_c
Not used on UDIMMs.
SDRAM data strobes
DQS0_t-DQS8_t
DQS0_c-DQS8_c
(positive line of differential pair)
SDRAM data strobes
RESET_n
Set DRAMs to a Known State
(negative line of differential pair)
SDRAM data masks/data bus inersion
(x8-based x72 DIMMs)
DM0_n-DM8_n,
DBI0_n-DBI8_n
SPD signals a thermal event has
occurred
EVENT_n
VTT
SDRAM clock (positive line of differen-
tial pair)
CK0_t, CK1_t
CK0_c, CK1_c
SDRAM I/O termination supply
Reserved for future use
SDRAM clock (positive line of differen-
tial pair)
RFU
1. Address A17 is not valid for x8 and x16 based SDRAMs. For UDIMMs, this connection pin is NC.
2. RAS_n is a multiplexed function with A16.
3. CAS_n is a multiplexed function with A15.
4. WE_n is a multiplexed function with A14.
Rev. 1.2 / Mar.2016
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