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HM6AQB36104BPL60 PDF预览

HM6AQB36104BPL60

更新时间: 2024-12-01 15:34:11
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器
页数 文件大小 规格书
26页 275K
描述
1MX36 QDR SRAM, 0.5ns, PBGA165, 15 X 17 MM, 1 MM PITCH, PLASTIC, FBGA-165

HM6AQB36104BPL60 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Contact Manufacturer零件包装代码:BGA
包装说明:15 X 17 MM, 1 MM PITCH, PLASTIC, FBGA-165针数:165
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.87
Base Number Matches:1

HM6AQB36104BPL60 数据手册

 浏览型号HM6AQB36104BPL60的Datasheet PDF文件第2页浏览型号HM6AQB36104BPL60的Datasheet PDF文件第3页浏览型号HM6AQB36104BPL60的Datasheet PDF文件第4页浏览型号HM6AQB36104BPL60的Datasheet PDF文件第5页浏览型号HM6AQB36104BPL60的Datasheet PDF文件第6页浏览型号HM6AQB36104BPL60的Datasheet PDF文件第7页 
HM66AQB36104/HM66AQB18204  
HM66AQB9404  
36-Mbit QDRTMII SRAM  
4-word Burst  
REJ03C0048-0100  
Rev.1.00  
Aug.23.2006  
Description  
The HM66AQB36104 is a 1,048,576-word by 36-bit, the HM66AQB18204 is a 2,097,152-word by 18-bit, and the  
HM66AQB9404 is a 4,194,304-word by 9-bit synchronous quad data rate static RAM fabricated with advanced CMOS  
technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a  
burst counter. All input registers controlled by an input clock pair (K and K) and are latched on the positive edge of K  
and K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high  
density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.  
Features  
1.8 V ± 0.1 V power supply for core (VDD  
1.4 V to VDD power supply for I/O (VDDQ  
DLL circuitry for wide output data valid window and future frequency scaling  
Separate independent read and write data ports with concurrent transactions  
100% bus utilization DDR read and write operation  
)
)
Four-tick burst for reduced address frequency  
Two input clocks (K and K) for precise DDR timing at clock rising edges only  
Two output clocks (C and C) for precise flight time and clock skew matching-clock and data delivered together to  
receiving device  
Internally self-timed write control  
Clock-stop capability with µs restart  
User programmable impedance output  
Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/5.0 ns (200 MHz)/6.0 ns (167 MHz)  
Simple control logic for easy depth expansion  
JTAG boundary scan  
Note: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress  
Semiconductor, IDT, NEC, Samsung, and Renesas Technology Corp.  
Rev.1.00 Aug 23, 2006 page 1 of 20  

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