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HM628512LTT-5SL PDF预览

HM628512LTT-5SL

更新时间: 2024-01-29 15:07:25
品牌 Logo 应用领域
HITACHI-METALS 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
15页 88K
描述
524288-word x 8-bit High Speed CMOS Static RAM

HM628512LTT-5SL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP32,.46
针数:32Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.78Is Samacsys:N
最长访问时间:55 ns其他特性:BATTERY BACK-UP OPERATION
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
JESD-609代码:e0长度:20.95 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:32字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP32,.46封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.000015 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.1 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

HM628512LTT-5SL 数据手册

 浏览型号HM628512LTT-5SL的Datasheet PDF文件第6页浏览型号HM628512LTT-5SL的Datasheet PDF文件第7页浏览型号HM628512LTT-5SL的Datasheet PDF文件第8页浏览型号HM628512LTT-5SL的Datasheet PDF文件第10页浏览型号HM628512LTT-5SL的Datasheet PDF文件第11页浏览型号HM628512LTT-5SL的Datasheet PDF文件第12页 
HM628512 Series  
Write Cycle  
HM628512  
-5  
-7A  
-7  
Min  
70  
60  
0
Parameter  
Symbol Min  
Max Min  
Max  
20  
20  
Max Unit  
Notes  
Write cycle time  
tWC  
tCW  
tAS  
55  
50  
0
20  
20  
55  
50  
0
25  
25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip selection to end of write  
Address setup time  
2
3
Address valid to end of write  
Write pulse width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
50  
40  
5
50  
40  
5
60  
50  
5
1, 8  
4
Write recovery time  
WE to output in high-Z  
Data to write time overlap  
Data hold from write time  
0
0
0
5, 6, 7  
25  
0
25  
0
30  
0
Output active from output in high-Z tOW  
Output disable to output in high-Z tOHZ  
5
5
5
6
0
0
0
5, 6  
Notes: 1. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later  
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high  
or WE going high. tWP is measured from the beginning of write to the end of write.  
2. tCW is measured from CS going low to the end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the earlier of WE or CS going high to the end of write cycle.  
5. During this period, I/O pins are in the output state so that the input signals of the opposite phase to  
the outputs must not be applied.  
6. This parameter is sampled and not 100% tested.  
7. tWHZ is defined as the time at which the outputs acheive the open circuit conditons and is not  
referred to output voltage levels.  
8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of  
data bus contention. tWP tDW min + tWHZ max  
9

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