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HM624100HCJP-10 PDF预览

HM624100HCJP-10

更新时间: 2024-11-26 22:32:55
品牌 Logo 应用领域
日立 - HITACHI 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
14页 66K
描述
4M High Speed SRAM (1-Mword x 4-bit)

HM624100HCJP-10 数据手册

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HM624100HC Series  
4M High Speed SRAM (1-Mword × 4-bit)  
ADE-203-1198 (Z)  
Preliminary  
Rev. 0.0  
Nov. 30, 2000  
Description  
The HM624100HC is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed  
access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing  
technology. It is most appropriate for the application which requires high speed and high density memory,  
such as cache and buffer memory in system. The HM624100HC is packaged in 400-mil 32-pin SOJ for high  
density surface mounting.  
Features  
Single 5.0 V supply : 5.0 V ± 10 %  
Access time 10 ns (max)  
Completely static memory  
No clock or timing strobe required  
Equal access and cycle times  
Directly TTL compatible  
All inputs and outputs  
Operating current : 140 mA (max)  
TTL standby current : 40 mA (max)  
CMOS standby ccurrent : 5 mA (max)  
: 1.2 mA (max) (L-version)  
Data retension current : 0.8 mA (max) (L-version)  
Data retension voltage : 2.0 V (min) (L-version)  
Center VCC and VSS type pinout  
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest  
Hitachi’s Sales Dept. regarding specification.  

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