Datasheet > HM5264165LTT-80

HM5264165LTT-80

更新时间： 2024-10-27 23:56:15

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
62页	757K
描述
x16 SDRAM

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数据手册

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HM5264165LTT-80 数据手册

HM5264165 Series

HM5264805 Series

HM5264405 Series

64M LVTTL interface SDRAM

125 MHz/100 MHz

1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank/

4-Mword × 4-bit × 4-bank

ADE-203-497C(Z)

Rev. 1.0

July 1, 1998

Description

The Hitachi HM5264165 is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi

HM5264805 is a 64-Mbit SDRAM organized as 2097512-word × 8-bit × 4 bank. The Hitachi HM5264405

is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to

the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features

•

3.3 V power supply

Clock frequency: 125 MHz/100 MHz (max)

LVTTL interface

Single pulsed RAS

4 banks can operate simultaneously and independently

Burst read/write operation and burst read/single write operation capability

Programmable burst length: 1/2/4/8/full page

2 variations of burst sequence

Sequential (BL = 1/2/4/8/full page)

Interleave (BL = 1/2/4/8)

•

Programmable CAS latency : 2/3

Byte control by DQM : DQM (HM5264805/HM5264405)

: DQMU/DQML (HM5264165)

Refresh cycles: 4096 refresh cycles/64 ms

2 variations of refresh

•

Auto refresh

Self refresh

12 3 4 5 6 7...62

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