Datasheet > HM5216805TT-12

HM5216805TT-12

更新时间： 2024-10-27 04:21:47

品牌	Logo	应用领域
日立 - HITACHI		动态存储器
页数	文件大小	规格书
60页	570K
描述
16 M LVTTL Interface SDRAM 100 MHz/83 MHz 1-Mword ⅴ 8-bit ⅴ 2-bank/2-Mword ⅴ 4-bit ⅴ 2-bank

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HM5216805TT-12 数据手册

HM5216805 Series,

HM5216405 Series

16 M LVTTL Interface SDRAM

100 MHz/83 MHz

1-Mword × 8-bit × 2-bank/2-Mword × 4-bit × 2-bank

ADE-203-304E (Z)

Rev. 5.0

November 1, 1997

Description

All inputs and outputs are referred to the rising edge of the clock input. The HM5216805 Series,

HM5216405 Series are offered in 2 banks for improved performance.

Features

•

3.3V Power supply

Clock frequency: 100 MHz/83 MHz (max)

LVTTL interface

Single pulsed RAS

2 Banks can operates simultaneously and independently

Burst read/write operation and burst read/single write operation capability

Programmable burst length: 1/2/4/8/full page

2 variations of burst sequence

Sequential (BL = 1/2/4/8/full page)

Interleave (BL = 1/2/4/8)

•

Programmable CAS latency: 1/2/3

Refresh cycles: 4096 refresh cycles/64 ms

2 variations of refresh

Auto refresh

Self refresh (L-version)

12 3 4 5 6 7...60

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型号	品牌	获取价格	描述	数据表
HM5216805TT-15	ETC	获取价格	x8 SDRAM
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HM5216805TT-B60	HITACHI	获取价格	Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
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