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HIP7010P

更新时间： 2024-01-15 11:24:37
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
20页 109K
描述
J1850 Byte Level Interface Circuit

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中文翻译

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HIP7010P 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：PLASTIC, MS-001AA, DIP-14
针数：14Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.86
JESD-30 代码：R-PDIP-T14JESD-609代码：e0
功能数量：1端子数量：14
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
标称供电电压：5 V表面贴装：NO
电信集成电路类型：INTERFACE CIRCUIT温度等级：AUTOMOTIVE
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子位置：DUALBase Number Matches：1

HIP7010P 数据手册

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HIP7010  
ADVANCE INFORMATION  
August 1996  
J1850 Byte Level Interface Circuit  
Features  
Description  
• Fully Supports VPW (Variable Pulse Width) Messaging  
Practices of SAE J1850 Standard for Class B Data  
Communications Network Interface  
The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a  
member of the Intersil family of low-cost multiplexed wiring  
ICs. The integrated functions of the HIP7010 provide the  
system designer with components key to building a “Class B”  
multiplexed communications network interface, which fully  
conforms to the VPW Multiplexed Wiring protocol specified  
in the SAE J1850 Standard. The HIP7010 is designed to  
interface with a wide variety of Host microcontrollers via a  
standard three wire, high-speed (1MHz), synchronous, serial  
interface. The HIP7010 automatically produces properly  
framed VPW messages, prepending the Start of Frame  
(SOF) symbol and calculating and appending the CRC  
check byte. All circuitry needed to decode incoming mes-  
sages, to validate CRC bytes, and to detect Breaks, End of  
Data (EOD), Idle bus, and illegal symbols is included. In-  
Frame Responses (IFRs) are fully supported for Type 1,  
Type 2, and Type 3 messages, with the appropriate Normal-  
ization Bit automatically generated. The HCMOS design  
allows proper opeSration at various input frequencies from  
2MHz to 12MHz. Connection to the J1850 Bus is via a Inter-  
sil HIP7020.  
- 3-Wire, High-Speed, Synchronous, Serial Interface  
• Reduces Wiring Overhead  
• Directly Interfaces with 68HC05 and 68HC11 Style SPI  
Ports  
• 1MHz, 8-Bit Transfers Between Host and HIP7010  
Minimize Host Service Requirements  
• Automatically Transmits Properly Framed Messages  
• Prepends SOF to First Byte and Appends CRC to Last  
Byte  
• Fail-Safe Design Including, Slow Clock Detection  
Circuitry, Prevents J1850 Bus Lockup Due to System  
Errors or Loss of Input Clock  
• Automatic Collision Detection  
• End of Data (EOD), Break, Idle Bus, and Invalid Symbol  
(Noise/Illegal Symbols) Detection  
• Supports In-Frame Responses with Generation of  
Normalization Bits (NB) for Type 1, Type 2, and Type 3  
Messages  
• Wait-For-Idle Mode Reduces Host Overhead During  
Non-Applicable Messages  
Ordering Information  
TEMP.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
PKG. NO.  
• Status Register Flags Provide Information on Current  
Status of J1850 Bus  
HIP7010P  
HIP7010B  
-40 +125 14 Lead Plastic DIP  
E14.3  
• Serial I/O Pins are Active Only During Transfers - Bus  
Available for Other Devices 95% of the Time  
• TEST Pin Provides Built-in-Test Capabilities for  
In-System Diagnostics and Factory Testing  
• High Speed (4X) Receive Mode for Production and  
Diagnostic Testing/Programming  
-40 +125 14 Lead Plastic SOIC (N) M14.15  
• Operates with Wide Range of Input Clock Frequencies  
• Power-Saving Power-Down Mode  
o
o
• Full -40 C to +125 C Operating Range  
• Single 3.0V to 6.0V Supply  
Pinout  
HIP7010 (SOIC, PDIP)  
TOP VIEW  
IDLE  
1
2
3
4
5
6
7
14 RDY  
VPWIN  
13 STAT  
12 CLK  
VPWOUT  
V
11 V  
DD  
SS  
RESET  
TEST  
10 SIN  
9
8
SOUT  
SCK  
SACTIVE  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3644.2  
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
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中文翻译

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