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HIP4020

更新时间: 2024-11-15 22:51:19
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英特矽尔 - INTERSIL 驱动器
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8页 69K
描述
Half Amp Full Bridge Power Driver for Small 3V, 5V and 12V DC Motors

HIP4020 数据手册

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HIP4020  
Half Amp Full Bridge Power Driver  
for Small 3V, 5V and 12V DC Motors  
June 1997  
Features  
Description  
• Two Independent Controlled Complementary In the Functional Block Diagram of the HIP4020, the four switches  
MOS Power Output Half H-Drivers (Full-Bridge) and a load are arranged in an H-Configuration so that the drive volt-  
for Nominal 3V to 12V Power Supply Operation  
age from terminals OUTA and OUTB can be cross-switched to  
change the direction of current flow in the load. This is commonly  
known as 4-quadrant load control. As shown in the Block Diagram,  
switches Q1 and Q4 are conducting or in an ON state when current  
flows from VDD through Q1 to the load, and then through Q4 to termi-  
nal VSSB; where load terminal OUTA is at a positive potential with  
respect to OUTB. Switches Q1 and Q4 are operated synchronously  
by the control logic. The control logic switches Q3 and Q2 to an open  
or OFF state when Q1 and Q4 are switched ON. To reverse the cur-  
rent flow in the load, the switch states are reversed where Q1 and Q4  
are OFF while Q2 and Q3 are ON. Consequently, current then flows  
from VDD through Q3, through the load, and through Q2 to terminal  
• Split ±Voltage Power Supply Option for Output  
Drivers  
• Load Switching Capabilities to 0.5A  
• Single Supply Range +2.5V to +15V  
• Low Standby Current  
• CMOS/TTL Compatible Input Logic  
• Over-Temperature Shutdown Protection  
• Over-Current Limit Protection  
VSSA, and load terminal OUTB is then at a positive potential with  
• Over-Current Fault Flag Output  
• Direction, Braking and PWM Control  
respect to OUTA.  
Terminals ENA and ENB are ENABLE Inputs for the Logic A and B  
Input Controls. The ILF output is an Over-Current Limit Fault Flag Out-  
put and indicates a fault condition for either Output A or B or both. The  
Applications  
V
DD and VSS are the Power Supply reference terminals for the A and  
• DC Motor Driver  
B Control Logic Inputs and ILF Output. While the VDD positive power  
supply terminal is internally connected to each bridge driver, the VSSA  
and VSSB Power Supply terminals are separate and independent from  
• Relay and Solenoid Drivers  
• Stepper Motor Controller  
• Air Core Gauge Instrument Driver  
• Speedometer Displays  
VSS and may be more negative than the VSS ground reference termi-  
nal. The use of level shifters in the gate drive circuitry to the NMOS  
(low-side) output stages allows controlled level shifting of the output  
drive relative to ground.  
• Tachometer Displays  
Ordering Information  
• Remote Power Switch  
TEMP.  
RANGE ( C)  
• Battery Operated Switch Circuits  
• Logic and Microcontroller Operated Switch  
o
PART NUMBER  
PACKAGE  
20 Ld SOIC  
PKG. NO.  
HIP4020IB  
-40 to 85  
M20.3  
Pinout  
Block Diagram  
HIP4020 SOIC  
VDD  
TOP VIEW  
ISENSE  
Q3  
1
2
3
4
5
6
7
8
9
NC  
ILF  
B2  
20  
NC  
ISENSE  
VDD  
19  
B1  
B2  
18 NC  
Q1  
OUTB  
OUTA  
ENB  
B1  
17 OUTB  
16 VSSB  
15 VSSA  
14 OUTA  
13 NC  
ENB  
A1  
TSENSE  
Q4  
ISENSE  
VSS  
ENA  
A1  
A2  
Q2  
ENA  
ISENSE  
ILF  
12  
A2  
VDD  
NC 10  
11 NC  
VSS  
VSSA  
VSSB  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3976.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1

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