HFA3101
®
Data Sheet
September 2004
FN3663.5
Gilbert Cell UHF Transistor Array
Features
The HFA3101 is an all NPN transistor array configured as a
Multiplier Cell. Based on Intersil’s bonded wafer UHF-1 SOI
• Pb-free Available as an Option
• High Gain Bandwidth Product (f ) . . . . . . . . . . . . . 10GHz
T
process, this array achieves very high f (10GHz) while
T
• High Power Gain Bandwidth Product . . . . . . . . . . . . 5GHz
maintaining excellent h and V matching characteristics
FE BE
that have been maximized through careful attention to circuit
design and layout, making this product ideal for
communication circuits. For use in mixer applications, the
cell provides high gain and good cancellation of 2nd order
distortion terms.
• Current Gain (h ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
FE
• Low Noise Figure (Transistor) . . . . . . . . . . . . . . . . . 3.5dB
• Excellent h and V Matching
FE BE
• Low Collector Leakage Current . . . . . . . . . . . . . . <0.01nA
• Pin to Pin Compatible to UPA101
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (°C)
PKG.
DWG. #
Applications
PACKAGE
8 Ld SOIC
• Balanced Mixers
HFA3101B
(H3101B)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
M8.15
M8.15
M8.15
M8.15
• Multipliers
HFA3101BZ
(H3101B) (Note)
8 Ld SOIC
(Pb-free)
• Demodulators/Modulators
• Automatic Gain Control Circuits
• Phase Detectors
HFA3101B96
(H3101B)
8 Ld SOIC Tape
and Reel
HFA3101BZ96
8 Ld SOIC Tape
• Fiber Optic Signal Processing
• Wireless Communication Systems
• Wide Band Amplification Stages
• Radio and Satellite Communications
• High Performance Instrumentation
(H3101B) (Note)
and Reel (Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
Pinout
HFA3101
(SOIC)
TOP VIEW
Q
Q
Q
Q
3 4
1
2
Q
Q
6
5
NOTE: Q and Q - 2 Paralleled 3µm x 50µm Transistors
5
6
Q , Q , Q , Q - Single 3µm x 50µm Transistors
1
2
3
4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 1998, 2004. All Rights Reserved
1
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