HFA3102
®
Data Sheet
July 14, 2005
FN3635.5
Dual Long-Tailed Pair Transistor Array
Features
The HFA3102 is an all NPN transistor array configured as
dual differential amplifiers with tail transistors. Based on
Intersil bonded wafer UHF-1 SOI process, this array
• High Gain-Bandwidth Product (f ) . . . . . . . . . . . . . 10GHz
T
• High Power Gain-Bandwidth Product. . . . . . . . . . . . 5GHz
• High Current Gain (h ) . . . . . . . . . . . . . . . . . . . . . . . 70
FE
achieves very high f (10GHz) while maintaining excellent
T
h
and V matching characteristics over temperature.
BE
FE
• Noise Figure (Transistor) . . . . . . . . . . . . . . . . . . . . . 3.5dB
• Low Collector Leakage Current . . . . . . . . . . . . . . <0.01nA
Collector leakage currents are maintained to under 0.01nA.
Ordering Information
• Excellent h and V Matching
FE BE
TEMP.
PKG.
• Pin-to-Pin to UPA102G
PART NUMBER RANGE (°C)
PACKAGE
DWG. #
• Pb-Free Plus Anneal Available (RoHS Compliant)
HFA3102B96
-40 to 85
-40 to 85
-40 to 85
14 Ld SOIC Tape M14.15
and Reel
Applications
HFA3102BZ
(Note)
14 Ld SOIC
(Pb-free)
M14.15
• Single Balanced Mixers
• Wide Band Amplification Stages
• Differential Amplifiers
HFA3102BZ96
(Note)
14 Ld SOIC Tape M14.15
and Reel (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Multipliers
• Automatic Gain Control Circuits
• Frequency Doublers, Tripplers
• Oscillators
• Constant Current Sources
• Wireless Communication Systems
• Radio and Satellite Communications
• Fiber Optic Signal Processing
• High Performance Instrumentation
Pinout/Functional Diagram
HFA3102 (SOIC)
TOP VIEW
14
13
12
11
10
9
8
Q
6
Q
Q
1
2
Q
Q
5
4
Q
3
1
2
3
4
5
6
7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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1
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