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HEF4073BT PDF预览

HEF4073BT

更新时间: 2024-11-05 11:12:23
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
11页 157K
描述
Triple 3-input AND gateProduction

HEF4073BT 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.64
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm逻辑集成电路类型:AND GATE
湿度敏感等级:1功能数量:3
输入次数:3端子数量:14
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260传播延迟(tpd):110 ns
座面最大高度:1.75 mm表面贴装:YES
技术:CMOS端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

HEF4073BT 数据手册

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HEF4073B  
Triple 3-input AND gate  
Rev. 4 — 6 October 2017  
Product data sheet  
1 General description  
The HEF4073B is a triple 3-input AND gate. The outputs are fully buffered for highest  
noise immunity and pattern insensitivity to output impedance variations.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to  
VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.  
2 Features and benefits  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
Inputs and outputs are protected against electrostatic effects  
Specified from -40 °C to +85 °C  
Complies with JEDEC standard JESD 13-B  
3 Ordering information  
Table 1.ꢀOrdering information  
Type number  
Package  
Temperature range Name  
-40 °C to +85 °C SO14  
Description  
Version  
HEF4073BT  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
4 Functional diagram  
3
1A  
4
6
9
1B  
1C  
2A  
2B  
2C  
3A  
3B  
3C  
1Y  
2Y  
3Y  
5
1
2
8
11  
12  
13  
10  
nA  
nB  
nC  
nY  
aaa-027563  
aaa-027562  
Figure 1.ꢀFunctional diagram  
Figure 2.ꢀLogic diagram (one gate)  
 
 
 
 

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