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HD74LS280P-E PDF预览

HD74LS280P-E

更新时间: 2024-11-12 13:08:15
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
6页 175K
描述
LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDIP14, 6.30 X 19.20 MM, 2.54 MM PITCH, PLASTIC, DIP-14

HD74LS280P-E 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.16系列:LS
JESD-30 代码:R-PDIP-T14长度:19.2 mm
逻辑集成电路类型:PARITY GENERATOR/CHECKER位数:9
功能数量:1端子数量:14
最高工作温度:75 °C最低工作温度:-20 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):50 ns
认证状态:Not Qualified座面最大高度:5.06 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL EXTENDED
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

HD74LS280P-E 数据手册

 浏览型号HD74LS280P-E的Datasheet PDF文件第2页浏览型号HD74LS280P-E的Datasheet PDF文件第3页浏览型号HD74LS280P-E的Datasheet PDF文件第4页浏览型号HD74LS280P-E的Datasheet PDF文件第5页浏览型号HD74LS280P-E的Datasheet PDF文件第6页 
HD74LS280  
9-bit Odd / Even Parity Generator / Checker  
REJ03D0475–0300  
Rev.3.00  
Jul.15.2005  
This parity generator / checker offers the designer a trade-off between reduced power consumption and high  
performance. Although the HD74LS280 is implemented without expander inputs, the corresponding function is  
provided by the availability of an input at pin 4 and the absence of any internal connection at pin 3.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-14 pin  
PRDP0014AB-B  
(DP-14AV)  
HD74LS280P  
HD74LS280FPEL  
P
PRSP0014DF-B  
(FP-14DAV)  
SOP-14 pin (JEITA)  
F
L (2,000 pcs/reel)  
Notes: Please consult the sales office for the above package avail
Pin Arrangement  
G
H
1
14  
13  
12  
11  
10  
9
VCC  
Inputs  
E
D
C
B
F
E
D
C
B
A
Inputs  
Even  
Σ Odd  
A
8
(Top view)  
Function Table  
Outputs  
Number of inputs A through I that are high  
Σ Even  
Σ Odd  
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
H
L
L
H
Rev.3.00, Jul.15.2005, page 1 of 5  

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