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HD74LS293 PDF预览

HD74LS293

更新时间: 2024-11-12 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器
页数 文件大小 规格书
8页 176K
描述
4-bit Binary Counter

HD74LS293 数据手册

 浏览型号HD74LS293的Datasheet PDF文件第2页浏览型号HD74LS293的Datasheet PDF文件第3页浏览型号HD74LS293的Datasheet PDF文件第4页浏览型号HD74LS293的Datasheet PDF文件第5页浏览型号HD74LS293的Datasheet PDF文件第6页浏览型号HD74LS293的Datasheet PDF文件第7页 
HD74LS293  
4-bit Binary Counter  
REJ03D0477–0300  
Rev.3.00  
Jul.15.2005  
This counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and divide-  
by-eight counter. This counter has a gated zero reset. To use the maximum count length of this counter, the B input is  
connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the  
appropriate function table.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbrevin  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0014AB-B  
(DP-14AV)  
HD74LS293P  
DILP-14 pin  
P
Pin Arrangement  
NC  
NC  
NC  
1
2
3
12  
11  
10  
9
CC  
R
R
B
A
0(2)  
0(1)  
QC  
Outputs  
Inputs  
A
QA  
Q
A
D
QD  
Outputs  
8
Q
(Top view)  
Function Table  
Reset / Count  
Reset Input  
Outputs  
R0 (1)  
H
R0 (2)  
H
QD  
QC  
QB  
QA  
L
L
L
L
L
X
Count  
Count  
X
L
Rev.3.00, Jul.15.2005, page 1 of 7  

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