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HD74HC73FPEL PDF预览

HD74HC73FPEL

更新时间: 2024-01-08 09:17:57
品牌 Logo 应用领域
瑞萨 - RENESAS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 107K
描述
Dual J-K Flip-Flops (with Clear)

HD74HC73FPEL 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:TSSOP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.52系列:HC/UH
JESD-30 代码:R-PDSO-G14长度:5 mm
逻辑集成电路类型:J-K FLIP-FLOP位数:2
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):190 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:NEGATIVE EDGE
宽度:4.4 mmBase Number Matches:1

HD74HC73FPEL 数据手册

 浏览型号HD74HC73FPEL的Datasheet PDF文件第2页浏览型号HD74HC73FPEL的Datasheet PDF文件第3页浏览型号HD74HC73FPEL的Datasheet PDF文件第4页浏览型号HD74HC73FPEL的Datasheet PDF文件第5页浏览型号HD74HC73FPEL的Datasheet PDF文件第6页浏览型号HD74HC73FPEL的Datasheet PDF文件第7页 
HD74HC73  
Dual J-K Flip-Flops (with Clear)  
REJ03D0548-0200  
(Previous ADE-205-420)  
Rev.2.00  
Oct 06, 2005  
Description  
The flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.  
Each flip-flop has independent, J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and  
accomplished by a low level on the input.  
Features  
High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-14 pin  
PRDP0014AB-B  
(DP-14AV)  
HD74HC73P  
P
PRSP0014DF-B  
(FP-14DAV)  
HD74HC73FPEL  
HD74HC73RPEL  
SOP-14 pin (JEITA)  
SOP-14 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Outputs  
Clear  
Clock  
J
X
L
K
X
L
Q
Q
H
L
X
L
H
No change  
L
H
L
H
L
H
L
H
H
H
X
X
X
H
L
H
X
X
X
Toggle  
No change  
No change  
No change  
H
L
H
H
H
H :  
L :  
X :  
High level  
Low level  
Irrelevant  
Rev.2.00, Oct 06, 2005 page 1 of 7  

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