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HD74HC533FPEL-E PDF预览

HD74HC533FPEL-E

更新时间: 2024-11-13 13:08:15
品牌 Logo 应用领域
瑞萨 - RENESAS 锁存器
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10页 119K
描述
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HD74HC533FPEL-E 数据手册

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HD74HC373, HD74HC533  
Octal D-type Transparent Latches (with 3-state outputs)  
Octal D-type Transparent Latches (with inverted 3-state outputs)  
REJ03D0619-0200  
(Previous ADE-205-498)  
Rev.2.00  
Mar 30, 2006  
Description  
When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of  
HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be  
retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control  
input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of  
the storage elements.  
Features  
High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
(Previous Code)  
PRDP0020AC-B  
(DP-20NEV)  
HD74HC373P  
P
HD74HC533P  
HD74HC373FPEL  
HD74HC533FPEL  
PRSP0020DD-B  
(FP-20DAV)  
SOP-20 pin (JEITA)  
SOP-20 pin (JEDEC)  
TSSOP-20 pin  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
ELL (2,000 pcs/reel)  
PRSP0020DC-A  
(FP-20DBV)  
HD74HC533RPEL  
HD74HC373TELL  
PTSP0020JB-A  
(TTP-20DAV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
HD74HC373  
Q
HD74HC533  
Output Control  
Enable G  
D
H
L
Q
L
L
L
H
H
L
H
L
No change  
Z
H
No change  
Z
L
X
X
H
X
Note: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance  
Rev.2.00 Mar 30, 2006 page 1 of 9  

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