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HD74HC4017RP PDF预览

HD74HC4017RP

更新时间: 2024-11-19 13:08:15
品牌 Logo 应用领域
日立 - HITACHI 计数器
页数 文件大小 规格书
8页 52K
描述
Ring Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 10-Bit, Up Direction, CMOS, PDSO16, FP-16DN

HD74HC4017RP 数据手册

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HD74HC4017  
Decade Counter/Divider  
Description  
The HD74HC4017 is a 5-stage divide-by-10 Johnson counter with ten decoded outputs and a carry-out bit.  
High-speed operation and spike-free outputs are obtained by use of the Johnson decade counter  
configuration.  
The ten decoded outputs are normally low and go high only at their respective decimal time periods. A  
high signal on Reset R asynchronously clears the decade counter and sets the carry output and Y0 high.  
With CE low, the count is advanced on a low-to-high transition at C input. Alternatively, if C is high, the  
count is advanced on a high-to-low transition at CE. Each decoded output remains high for one full clock  
cycle. The carry output is high while Q0, Q1, Q2, Q3 or Q4 is high, then is low while Q5, Q6, Q7, Q8 or Q9 is  
high.  
Features  
High Speed Operation  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  

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