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HD74HC4017P-E PDF预览

HD74HC4017P-E

更新时间: 2024-11-19 13:01:19
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瑞萨 - RENESAS 计数器
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HD74HC4017P-E 数据手册

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HD74HC4017  
Decade Counter / Divider  
REJ03D0644-0200  
(Previous ADE-205-530)  
Rev.2.00  
Mar 30, 2006  
Description  
The HD74HC4017 is a 5-stage divide-by-10 Johnson counter with ten decoded outputs and a carry-out bit. High-speed  
operation and spike-free outputs are obtained by use of the Johnson decade counter configuration.  
The ten decoded outputs are normally low and go high only at their respective decimal time periods. A high signal on  
Reset R asynchronously clears the decade counter and sets the carry output and Y0 high. With CE low, the count is  
advanced on a low-to-high transition at C input. Alternatively, if C is high, the count is advanced on a high-to-low  
transition at CE. Each decoded output remains high for one full clock cycle. The carry output is high while Q0, Q1, Q2,  
Q3 or Q4 is high, then is low while Q5, Q6, Q7, Q8 or Q9 is high.  
Features  
High Speed Operation  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
(Previous Code)  
PRDP0016AE-B  
(DP-16FV)  
HD74HC4017P  
P
PRSP0016DH-B  
(FP-16DAV)  
HD74HC4017FPEL  
HD74HC4017RPEL  
SOP-16 pin (JEITA)  
SOP-16 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0016DG-A  
(FP-16DNV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
C
L
CE  
X
R
L
L
H
L
L
L
L
Decode Output = n  
n
n
X
X
H
X
Q0  
n + 1  
n
L
X
X
n
H
n + 1  
Notes: 1. X: Don’t care  
2. If n < 5 Carry = “H”, Otherwise = “L”  
Rev.2.00 Mar 30, 2006 page 1 of 10  

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