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HD74ALVCH16245 PDF预览

HD74ALVCH16245

更新时间: 2024-11-09 05:35:11
品牌 Logo 应用领域
瑞萨 - RENESAS 总线收发器
页数 文件大小 规格书
9页 123K
描述
6-bit Bus Transceivers with 3-state Outputs

HD74ALVCH16245 数据手册

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HD74ALVCH16245  
6-bit Bus Transceivers with 3-state Outputs  
REJ03D0049-0500Z  
(Previous ADE-205-134C(Z))  
Rev.5.00  
Oct.02.2003  
Description  
The HD74ALVCH16245 is designed for asynchronous communication between data buses. The control  
function implementation minimizes external timing requirements. This device can be used as two 8-bit  
transceivers or one 16-bit transceiver. It allow data transmission from the A bus to the B bus or from the B  
bus to the A bus depending upon the logic level at the direction control (DIR) input. The output enable  
(OE) input can be used to disable the device so that the buses are effectively isolated. Active bus hold  
circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Features  
VCC = 2.3 V to 3.6 V  
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)  
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors  
Function Table  
Inputs  
Operation  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
H : High level  
L : Low level  
X : Immaterial  
Rev.5.00, Oct.02.2003, page 1 of 8  

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